- BTBUpdate only occurs on mispredicts now.
- RASUpdate broken out from BTBUpdate (allows RASUpdate to be performed in
Decode).
- Added optional 2nd CAM port to BTB for updates (for when updates to the
BTB may occur out-of-order).
- Fixed resp.mask bit logic.
- Global history only contains branches.
- Only update BHT and history on BTB hits.
- Gate off speculative update on stall or icmiss.
- Fixed bug where BHT updates were delayed a cycle.
- No longer update global history in fetch stage.
- Only update global history when instruction is a branch.
- Does allow for the possibility of back-to-back branches to see
slightly different histories on subsequent executions.
- Updated in fetch speculatively.
* Updates gated off by cpu.resp.fire().
* BTB direction factored into history update.
- All branches update the BHT.
- Each instruction carries history; index into BHT is recomputed by
passing in mem_reg_pc.
BTB entries reference a small number of unique pages, so we separate the
storage of pages from indices. This makes much larger BTBs feasible. It's
easy to exacerbate cycle time this way, so one-hot encoding is used as needed.
