89139a9492
Plic: split constants from variables used in config string
2016-10-31 11:42:13 -07:00
11121b6f4c
rocket: convert scratchpad to TL2
2016-10-31 11:42:13 -07:00
dddb50a942
BuildTiles: convert to LazyTile
2016-10-31 11:42:13 -07:00
f8a0829134
rocketchip: remove clint; it moves into coreplex
2016-10-31 11:42:13 -07:00
5090ff945b
DebugModule: Be more paranoid about addressing corner cases.
2016-10-31 11:42:13 -07:00
b99662796d
PLIC: converted to TL2
2016-10-31 11:42:13 -07:00
bddfa4d69b
Debug: make address configurable
2016-10-31 11:42:13 -07:00
c3dacca39a
rocketchip: remove pbus; TL2 has swallowed it completely
2016-10-31 11:42:08 -07:00
10d084b9f3
DebugModule: Use the power of RegisterRouter to simplify the DebugROM code.
2016-10-31 11:41:18 -07:00
3df797fcab
rocketchip: replace TL1 MMIO with an example of TL2 MMIO
2016-10-31 11:41:18 -07:00
650f6fb23f
diplomacy: add BlindNodes for use as external ports
2016-10-31 11:41:18 -07:00
0edcd3304a
diplomacy Nodes: leave flipping to the MixedNode implementation
2016-10-31 11:41:18 -07:00
082f338432
diplomacy Nodes: remove useless indirection
2016-10-31 11:41:18 -07:00
ec2d23b8b7
rocketchip: Bundle-slices need access to the outer LazyModule
...
We need this change in order for some ports to use parameters that result
from LazyModule diplomacy.
Now you can eat your cake too!
2016-10-31 11:41:18 -07:00
0ae45d0f24
rocketchip: bundle (=> B) need not be delayed; Module is constructed later
2016-10-31 11:41:18 -07:00
0dbda2f07d
rocketchip: remove obsolete pDevices used during TL1=>2 migration
2016-10-31 11:41:18 -07:00
af924d8c51
DebugModule: Instantiate TL2 DebugModule in BaseCoreplex
2016-10-31 11:41:18 -07:00
d530ef7236
DebugModule: translate to TL2 with {32,64}-bit XLen width
2016-10-31 11:41:18 -07:00
3e08d615f0
Merge pull request #427 from ucb-bar/put-after-release-bugfix
...
Fix issue with PutBlock and Release in BroadcastHub
2016-10-31 11:28:24 -07:00
f0e9a2a081
Fix PutBlock after Release bug
...
There is logic in the broadcast hub to skip the outer acquire if there
is an outgoing release, since the data will be written out through the
release channel. However, this will cause an issue in the case of
PutBlock requests. If the tail beats of the PutBlock show up after the
outer release has already been sent, the data will be corrupted.
The fix is to make the outer release block if there are pending
inner PutBlock beats.
2016-10-28 18:26:34 -07:00
cb81ea516c
add regression test for put-after-release bug
2016-10-28 18:26:34 -07:00
fa8844d5c3
properly use rocket MT_ constants in regression tests
2016-10-28 18:26:34 -07:00
f8bb67ab8f
Bind some Make vars early to avoid redundant evaluation
2016-10-28 11:56:13 -07:00
f3c726033a
Make all Chisel invocations depend on FIRRTL_JAR
2016-10-28 11:56:05 -07:00
2b65478f3a
bump chisel/firrtl
2016-10-28 00:36:53 -07:00
e45b41b4b6
Don't rely on SeqMem output after read-enable is low
2016-10-27 23:44:10 -07:00
190a8b9dd3
Update README.md to reflect firrtl and riscv-tools changes
2016-10-27 11:40:09 -07:00
8c538f548b
Merge pull request #422 from ucb-bar/use-random-port-for-jtag-vpi
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Use random, unused port for JTAG VPI
2016-10-26 13:16:28 -07:00
cc5b7d1eb6
Bump riscv-tools.
2016-10-26 11:40:49 -07:00
183ae58704
Use a random port number for JTAG VPI.
2016-10-26 11:40:45 -07:00
900a7bbcf1
add PutAtomic support to width adapter
2016-10-26 09:58:26 -07:00
47887c40ac
Merge pull request #421 from ucb-bar/fix_async_fifo
...
Fixed AsyncFifo with reset messaging
2016-10-25 18:22:27 -07:00
fc5eb7cc64
Fixed AsyncFifo with reset messaging
2016-10-25 16:45:08 -07:00
fd2d48acda
lazy_module: If the user actually specifies a name, just use it without appending module name.
2016-10-25 15:58:09 -07:00
a807c922d0
diplomacy: take names from the outermost common node
2016-10-25 15:58:09 -07:00
fee67c4abf
diplomacy: add methods to find {out,in}ner-most common node
2016-10-25 15:58:09 -07:00
67ab27f5a5
diplomacy: guess the LazyModule name from the containing class
2016-10-25 15:58:09 -07:00
4d50733548
tilelink2 ToAXI4: use helper method for a_last ( #418 )
2016-10-25 10:16:42 -07:00
7dc97674d6
rocketchip: include an socBus between l1tol2 and periphery ( #415 )
...
Sometimes we have high performance devices that go inbetween.
2016-10-24 23:56:09 -07:00
a5ac106bb8
axi4 ToTL: fix decode error arbitration ( #417 )
...
When selecting between error generation on R and real data on R,
correctly calculate the R backpressure.
This bug manifests when a valid request is immediately followed by
an invalid request, wedging the R channel.
2016-10-24 22:15:19 -07:00
4c815f7958
tilelink2 Parameters: fix {contains,supports}Safe ( #416 )
...
When there is only one manager, you still want to know if the address
was wrong on the link to that manager!
2016-10-24 20:37:04 -07:00
b9a082223c
Merge pull request #414 from ucb-bar/sanity-check-debug
...
Sanity check compile-time vs simulation-time options
2016-10-24 15:58:29 -07:00
f382ee70da
Sanity check compile-time vs simulation-time options
...
If user compiles without +define+DEBUG but then requests +vcdfile at
simulation time, that request would be silently ignored. This changes
it to a fatal error.
It's good philosophy to treat plusargs like +vcdfile as commands, not
suggestions, and die immediately if they cannot be honored, instead of
silently ignoring them. Otherwise the user sits through the entire
simulation and then is left scratching his head wondering where his
waveforms are.
2016-10-24 14:45:34 -07:00
737cf82478
Print out seed if we can ( #412 )
...
Now that we have ifdef VCS in here lets use it for something more than compatibility
2016-10-24 12:36:29 -07:00
bc01f85164
Merge pull request #406 from ucb-bar/incisive-fixes
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More Cadence Incisive fixes
2016-10-24 10:48:24 -07:00
9326cfd64a
Merge branch 'master' into incisive-fixes
2016-10-23 23:08:01 -07:00
288d7169ae
Bump firrtl and update vsim Makefrag-verilog ( #409 )
2016-10-23 23:07:47 -07:00
8bfd6bcd4d
axi4: ensure we accept AR before reporting R ( #411 )
2016-10-21 21:02:05 -07:00
cb8878c931
Don't build any hurricane branches
...
Don't mean to eat up travis bandwidth but shared branches sometimes get made.
2016-10-21 16:26:41 -07:00
85f3788ab5
initialize s2_hit to solve #401
2016-10-21 14:53:55 -07:00
