cf3c6fa277
add STOP_COND to emulator & match vsim PRINTF_COND
2016-09-09 11:07:17 -07:00
ba4b3e14cc
remove remaining dramsim2 files
2016-09-04 17:25:24 -07:00
08089f695d
allow configuration to be in separate project from test harness
2016-09-01 10:28:07 -07:00
93c801f598
Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. ( #227 )
2016-08-25 17:26:28 -07:00
4f388add67
More accurate conditional include of generated .d make fragment ( #222 )
2016-08-25 14:42:04 -07:00
ed827678ac
Write test harness in Chisel
...
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected). However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary. Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.
This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence. The main blocker is the lack of Verilog parameterization for
BlackBox. It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL. But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
dd1fed41b6
generate BootROM contents from assembly code
2016-08-05 16:39:21 -07:00
9751ea0f35
Fix Verilator VCD ( #157 )
2016-07-09 02:37:39 -07:00
32ee5432dd
Fix testing of DefaultSmallConfig; bump rocket et al
2016-07-07 21:23:49 -07:00
f1cbb2ff77
Turn up optimization for Verilator compilation
2016-06-28 14:12:46 -07:00
568bfa6c50
Purge legacy HTIF things
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The SCR file is gone, too, because it was tightly coupled. The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
daa0f3038f
invoke firrtl jar directly in order to control heap memory usage
2016-06-20 13:02:31 -07:00
4a8e6c773a
Fix +verbose flag for verilator
2016-06-17 21:09:08 -07:00
25ade44fe3
Don't build the Verilator man pages ( #141 )
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These failed for Andrew earlier. While it might be paranioa, there's
really no reason to build the man pages so we might as well not bother.
2016-06-16 10:13:21 -07:00
1525b4717e
Install Verilator when building the emulator
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We need a fairly new version of Verilator, so I just added a rule to
download and install it on all systems.
2016-06-14 21:21:43 -07:00
571b5b2093
Prevent sbt from running multiple times in emulator
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If you have multi-target rules that don't have %s in them, make
interprets that as "run this recipe multiple times, once to produce each
target". If you have %s in the rules, then make interprets it as "run
this recipe once to produce all targets". We want the second one.
2016-06-14 11:59:20 -07:00
3ce8dbb6e5
fix make error mixing implicit and normal rules
2016-06-14 11:59:20 -07:00
99b257316e
replace emulator with verilator for chisel3
2016-06-08 02:43:54 -07:00
e82c080c3c
Add blocking D$
2016-05-25 11:09:50 -07:00
f52fc655a5
remove zscale
2016-05-19 09:43:15 -07:00
46bbbba5e6
New address map
2016-04-30 20:59:36 -07:00
85cc632d5d
fix emulator debug build
2016-02-19 23:13:57 -08:00
db9de94588
Generate and use SCR address header files
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This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
07f0e6be94
Don't re-generate the .d files on "make clean"
2015-11-12 00:41:55 -08:00
bbf14ddc01
use definitions in consts header whenever possible
2015-11-05 10:48:32 -08:00
ba5a6af05c
correctly stripe data across memory channels in simulation
2015-11-05 10:48:32 -08:00
dcef020ca0
get multichannel simulation working in emulator
2015-11-05 10:48:32 -08:00
996670a4a6
Point to correct Chisel commit
2015-10-01 10:31:29 -07:00
c2344ee2bc
Added generated-src-debug to make clean target
2015-09-11 19:07:33 -07:00
8f71c4da2d
Reintroduced multiple emulator backend directories
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Fixes a "make -j" concurrency bug due to deleting files that another
parallel rule depends on.
2015-09-10 17:14:23 -07:00
ee531dc97e
Add missing changes to emulator/Makefile
2015-07-29 18:15:21 -07:00
bd4ff35a4b
Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS
2015-07-22 11:49:10 -07:00
a99b1e3a01
append config name to generated Makefrag filename
2015-07-17 12:34:49 -07:00
407d8e473e
first cut at parameter-based testing
2015-07-13 14:54:26 -07:00
854fd64fba
Added optional Makefile includes for private chip repos
2015-07-06 17:15:27 -07:00
d3ccec1044
Massive update containing several months of changes from the now-defunct private chip repo.
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* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
2015-07-02 14:43:30 -07:00
879a4a0bcd
Update Makefile
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Change default shell to bash shell.
2015-04-06 15:05:43 -07:00
484648d9c7
Changed CONFIG from a recursively expanded variable to a conditionally
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assigned variable, allowing users to define CONFIG external to Makefile
2014-09-17 11:12:02 -07:00
275b72368b
add CONFIG to the name of simulator executable
2014-09-11 22:11:58 -07:00
cfecd8832d
tease out reference-chip specific stuff
2014-09-09 20:49:28 -07:00
82467313dd
merge in rocketchip changes from master
2014-09-02 13:51:57 -07:00
c03c09ec31
update for rocket-chip release
2014-08-31 20:26:55 -07:00
0ca24a5d91
fix debug flags
2014-08-12 10:35:39 -07:00
08d81d0892
First cut at using new chisel parameters for toplevel parameters and fpu
2014-08-01 18:09:37 -07:00
6808245bb5
Timeout cycles now defined in toplevel Makefrag in order to allow for easier alteration when debugging.
2014-02-12 16:50:13 -08:00
fc52840ce2
move timeout in Makefile to a variable
2014-01-31 16:52:59 -08:00
e9d3a650a4
Speed up C++ compilation
2014-01-31 12:25:19 -08:00
fb827abbfa
Use dynamic fesvr library
2014-01-28 03:50:19 -08:00
8c380a7c3a
Abort "make run" when tests fail
2013-10-29 13:25:57 -07:00
b7d7ced41b
Update to new ISA
2013-09-21 06:40:23 -07:00
