Henry Cook d3ccec1044 Massive update containing several months of changes from the now-defunct private chip repo. ... * Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API. * Additional tests. * New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit * Updated TileLink protocol, NASTI protocol SHIMs. * Lays groundwork for multiple top-level memory channels, superscalar fetch. * Bump all submodules.		2015-07-02 14:43:30 -07:00
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dramsim2_ini	Added dramsim2 memory model to the emulator backend	2012-10-14 14:06:28 -07:00
.gitignore	add CONFIG to the name of simulator executable	2014-09-11 22:11:58 -07:00
Makefile	Massive update containing several months of changes from the now-defunct private chip repo.	2015-07-02 14:43:30 -07:00