riscv/rocket-chip
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First cut at using new chisel parameters for toplevel parameters and fpu

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This commit is contained in:
Adam Izraelevitz
2014-08-01 18:09:37 -07:00
parent fcd68364ff
commit 08d81d0892
5 changed files with 80 additions and 78 deletions
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8
emulator/Makefile
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@ -2,6 +2,8 @@ all: emulator
base_dir = ..
sim_dir = .
PROJECT = referencechip
CONFIG = DefaultCPPConfig
include $(base_dir)/Makefrag
@ -15,14 +17,14 @@ LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L. -ldramsim -lfes
OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir emulator/generated-src
CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir emulator/generated-src --configInstance $(PROJECT).$(CONFIG)
CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug
generated-src/$(MODEL).h: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala
cd $(base_dir) && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS)"
cd $(base_dir) && $(SBT) "project $(PROJECT)" "elaborate $(CHISEL_ARGS)"
generated-src-debug/$(MODEL).h: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala
cd $(base_dir) && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS_DEBUG)"
cd $(base_dir) && $(SBT) "project $(PROJECT)" "elaborate $(CHISEL_ARGS_DEBUG)"
$(MODEL).o: %.o: generated-src/%.h
$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls generated-src/$(MODEL)-*.cpp))