riscv/rocket-chip
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a59fc3bdaa
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511 Commits

Author SHA1 Message Date
Andrew Waterman
a59fc3bdaa Teach MulDiv to do either mul-only or div-only by setting unroll=0 2018-02-06 14:03:17 -08:00
Andrew Waterman
69441930b5 Rationalize ALU function encoding 
MULHSU and MULHU should match their ISA funct3 encodings to slightly
reduce HW cost.
 2018-02-06 14:00:37 -08:00
solomatnikov
5294523551
Keep io.cpu.s1_data for visibility (#1218) 2018-01-31 14:31:42 -08:00
Jacob Chang
f4853c4f63
Add cover properties to Core CSRs (#1212) 2018-01-30 00:01:19 -08:00
Andrew Waterman
b5ff853e86
Sign-extend the depc CSR (#1209) 2018-01-26 12:07:33 -08:00
Andrew Waterman
8d8e4e1399
Merge pull request #1196 from freechipsproject/interrupt-cover 
Cover all exceptions and interrupts
 2018-01-25 18:06:13 -08:00
Andrew Waterman
d2399b6d0e Cover all exceptions and interrupts 2018-01-25 16:14:56 -08:00
Andrew Waterman
a2ca82f92c Add VM covers 2018-01-23 16:13:35 -08:00
Henry Cook
24c1235500 rocket: add address to tlb permissions require msgs 2018-01-18 10:31:51 -08:00
Jacob Chang
80ca018e3a
Add cover points for BusErrorUnit (#1193) 2018-01-15 18:00:29 -08:00
Henry Cook
f5211765e9
Merge pull request #1177 from freechipsproject/dont-touch-2 
Make more use of chisel3.experimental.DontTouch
 2018-01-09 15:13:55 -08:00
pentin-as
c152962642 Dual-port RAM replaced with single-port RAM for tag_array in HellaCache (#1181) 
In accordance with https://github.com/freechipsproject/chisel3/issues/752
 2018-01-09 13:06:43 -08:00
Andrew Waterman
ad0b9a0b1b Reduce cases in which FENCE.I must flush D$ 
Memory regions that are uncacheable or have get/put effects should not
reside in the D$, so there is no need to flush them.
 2018-01-05 13:58:14 -08:00
Henry Cook
4853d1355f rocket: dontTouch HellaCache.io.cpu.resp 2018-01-05 12:50:24 -08:00
Andrew Waterman
206892899f
Merge pull request #1171 from freechipsproject/fix-msb-check 
Enforce physical-address canonicalization
 2018-01-03 12:06:18 -08:00
Andrew Waterman
ee1a9485df Enforce physical-address canonicalization 
When xLen > paddrBits, enforce that physical addresses are zero-extended.
This works by checking that the _virtual_ address is _sign_-extended, then
checking that its sign is positive.
 2018-01-02 18:47:30 -08:00
Andrew Waterman
7c9a1b0265 Correctly check for virtual-address canonicalization 
The previous check was necessary but not sufficient.
 2018-01-02 18:41:25 -08:00
Henry Cook
b0e1bc3071 tile: cake reduction 
* merge HasScratchpadSlavePort into RocketTile
* merge CanHaveSharedFPUModule into BaseTileModule
 2018-01-02 17:49:08 -08:00
Henry Cook
efe7165b54 tile: BaseTile refactor, pt 2 
* 2 layer cake
* no more bundle traits, only call to IO
 2018-01-02 15:37:31 -08:00
Henry Cook
1cd018546c tile: BaseTile refactor, pt 1 
* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
 2017-12-26 11:04:15 -08:00
Henry Cook
895c4b9261
Revert "ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144)" (#1162) 
This reverts commit a542ae687e.
 2017-12-19 12:16:26 -08:00
Jacob Chang
09160d0cd5
Changed label for DCache and ICache error covers + take away exclusio… (#1155) 
* Changed label for DCache and ICache error covers + take away exclusion that shouldn't be there

* rocket: add d-channel error to I$
 2017-12-13 20:16:36 -08:00
Wesley W. Terpstra
a542ae687e
ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144) 2017-12-08 17:35:14 -08:00
Andrew Waterman
676110bc1f Add cover for a1ebe6da4d 2017-12-07 21:03:42 -08:00
Andrew Waterman
a1ebe6da4d Prevent frontend deadlock fetching from uncacheable memory 
After detecting a corrupted BTB, don't speculatively update it until
the next non-speculative fetch.  This prevents the frontend from replaying
forever.
 2017-12-07 18:56:06 -08:00
Jacob Chang
ec3789b365
Add Cross Cover Property Library (#1149) 
Add cover points related to memory error to I/D Cache
 2017-12-07 18:46:10 -08:00
Andrew Waterman
5c204f98d5
When writing full words to ITIM, ECC errors are correctable (#1148) 
* When writing full words to ITIM, ECC errors are correctable

* Disable D$ tag reset state machine when using scratchpad
 2017-12-07 16:00:26 -08:00
Richard Xia
50de991f18 Fix typo in breakpoint cover property. 2017-12-04 14:04:24 -08:00
Henry Cook
71ddd797bf
Merge pull request #1138 from freechipsproject/cover_tag_ecc_error_during_fence_i 
Added coverage point to cover the case when ECC error happens during …
 2017-12-01 18:00:11 -08:00
Gleb Gagarin
7c2df9f0bf Cover the case when there is an ECC error in DCache data array during fence.i execution 2017-12-01 16:28:28 -08:00
Gleb Gagarin
74bd61c556 Added coverage point to cover the case when ECC error happens during fence.i execution 2017-12-01 15:50:31 -08:00
Richard Xia
a447343074
Merge pull request #1129 from freechipsproject/add-exception-cover-properties 
Add cover properties for exceptions in the core.
 2017-11-30 16:23:14 -08:00
Richard Xia
4bd9c477ea Add cover properties for ECALL exceptions. 2017-11-30 14:27:04 -08:00
Richard Xia
29c70501f2 Add cover properties for exceptions in the core. 2017-11-30 14:27:04 -08:00
Andrew Waterman
890528c641 Avoid data corruption under correctable tag error during flush 
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
 2017-11-29 16:09:44 -08:00
Andrew Waterman
34d86ef665 Revert "Avoid data corruption under correctable tag error during flush (#1130)" 
This reverts commit 44eb4d12b5.
 2017-11-29 16:09:30 -08:00
Andrew Waterman
44eb4d12b5 Avoid data corruption under correctable tag error during flush (#1130) 
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
 2017-11-29 09:42:00 -08:00
Andrew Waterman
5155eb6059
Don't emit writeback state machine logic for scratchpad (#1127) 
Firrtl can't DCE it because it would require analyzing the state machine.
 2017-11-22 18:40:02 -06:00
Yunsup Lee
a60d7d419d icache: add a couple cover points for I$ and ITIM iteraction 2017-11-20 13:14:38 -08:00
Andrew Waterman
5e94884f09 Fix ITIM deallocation during I$ refill causing data corruption 
Deallocation can change repl_way, which violates the assumption that it
remains constant throughout refill.

The workaround described in commit 3db066303b
still suffices, provided only the hart that owns the ITIM changes the ITIM
allocation.

This subsumes commit 3db066303b.
 2017-11-20 12:30:40 -08:00
Andrew Waterman
66b7a8a5ed Revert "Fix ITIM bug overwriting I$ contents when deallocating ITIM (#1079)" 
This reverts commit 3db066303b.
 2017-11-20 12:26:04 -08:00
Henry Cook
f3575404c0 tile: bus blocker needs to know width :( 2017-11-17 20:17:17 -08:00
Henry Cook
b625e68360
tile: put a BasicBusBlocker inside RocketTile (#1115) 
...instead of on the master side of the system bus.

People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
 2017-11-17 17:26:48 -08:00
Wesley W. Terpstra
7cfb69e2d5 Queue: silence some warnings 2017-11-14 15:09:09 -08:00
Henry Cook
7098ebf439
rocket: fix itim GetPropertyByHartId (#1109) 
needs to use RocketTileParams.hartid instead of zipWithIndex
 2017-11-13 19:25:20 -08:00
Andrew Waterman
4ebca73d59 Provide option to support AMOs only on I/O, not DTIM/D$ 2017-11-09 17:45:53 -08:00
Andrew Waterman
efdb418559
Merge pull request #1098 from freechipsproject/frontend 
Frontend improvements
 2017-11-09 17:44:38 -08:00
Andrew Waterman
d0c6cbba6b Improve frontend branch prediction 
- Put correctness responsibility on Frontend, not IBuf, for improved
  separation of concerns.  Frontend must detect case that the BTB
  predicts a taken branch in the middle of an instruction.

- Pass BTB information down pipeline unconditionally, fixing case that
  screws up the branch history when the BTB misses and the instruction
  is misaligned.

- Remove jumpInFrontend option; it's now unconditional.

- Default to one-bit counters in the BHT.  For tiny BHTs like these, it's
  more resource efficient to have a larger index space than to have
  hysteresis.
 2017-11-09 00:00:56 -08:00
Andrew Waterman
bb9d8264e2 "Correct" ITIM uncorrectable errors 
This permits forward progress when a core wants to handle its own
uncorrectable ITIM errors.  Previously, another core had to do it.
 2017-11-08 22:15:03 -08:00
Andrew Waterman
5c1b34d854 Don't report a TL error if overwriting a whole ITIM word 2017-11-08 22:15:03 -08:00