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ALU.scala
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Don't route branch comparison result through ALU output mux
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2017-10-07 17:36:24 -07:00 |
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AMOALU.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Breakpoint.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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BTB.scala
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Improve frontend branch prediction
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2017-11-09 00:00:56 -08:00 |
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BusErrorUnit.scala
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Add cover points for BusErrorUnit (#1193)
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2018-01-15 18:00:29 -08:00 |
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Consts.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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CSR.scala
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Add cover properties for ECALL exceptions.
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2017-11-30 14:27:04 -08:00 |
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DCache.scala
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Reduce cases in which FENCE.I must flush D$
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2018-01-05 13:58:14 -08:00 |
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Decode.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Events.scala
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Add method to print perf events
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2017-07-25 15:19:16 -07:00 |
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Frontend.scala
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tile: BaseTile refactor, pt 2
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2018-01-02 15:37:31 -08:00 |
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HellaCache.scala
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Merge pull request #1177 from freechipsproject/dont-touch-2
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2018-01-09 15:13:55 -08:00 |
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HellaCacheArbiter.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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IBuf.scala
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Improve frontend branch prediction
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2017-11-09 00:00:56 -08:00 |
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ICache.scala
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tile: BaseTile refactor, pt 1
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2017-12-26 11:04:15 -08:00 |
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IDecode.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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Instructions.scala
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Add RVC instruction patterns
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2017-07-25 15:19:16 -07:00 |
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Multiplier.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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NBDcache.scala
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tilelink: split Acquire into Acquire{Block,Perm} (#1030)
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2017-10-05 12:49:49 -07:00 |
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package.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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PMP.scala
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Move microarchitecture-neutral params from Rocket to Core
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2017-10-03 17:34:18 -07:00 |
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PTW.scala
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tile: BaseTile refactor, pt 2
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2018-01-02 15:37:31 -08:00 |
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RocketCore.scala
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Correctly check for virtual-address canonicalization
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2018-01-02 18:41:25 -08:00 |
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RVC.scala
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Expand C.UNIMP correctly (#1052)
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2017-10-12 14:00:14 -07:00 |
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ScratchpadSlavePort.scala
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tile: cake reduction
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2018-01-02 17:49:08 -08:00 |
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SimpleHellaCacheIF.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
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TLB.scala
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Enforce physical-address canonicalization
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2018-01-02 18:47:30 -08:00 |
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TLBPermissions.scala
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rocket: add address to tlb permissions require msgs
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2018-01-18 10:31:51 -08:00 |
