Andrew Waterman 890528c641 Avoid data corruption under correctable tag error during flush ...

This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.

2017-11-29 16:09:44 -08:00

..

ALU.scala

Don't route branch comparison result through ALU output mux

2017-10-07 17:36:24 -07:00

AMOALU.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

Breakpoint.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

BTB.scala

Improve frontend branch prediction

2017-11-09 00:00:56 -08:00

BusErrorUnit.scala

Provide separate masks for local & global BusErrorUnit interrupts

2017-11-06 18:03:59 -08:00

Consts.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

CSR.scala

Don't permit vectoring of high interrupts

2017-11-07 01:59:30 -08:00

DCache.scala

Avoid data corruption under correctable tag error during flush

2017-11-29 16:09:44 -08:00

Decode.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

Events.scala

Add method to print perf events

2017-07-25 15:19:16 -07:00

Frontend.scala

Improve frontend branch prediction

2017-11-09 00:00:56 -08:00

HellaCache.scala

coreplex: first cut at using RocketCrossingParams

2017-10-10 12:02:04 -07:00

HellaCacheArbiter.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

IBuf.scala

Improve frontend branch prediction

2017-11-09 00:00:56 -08:00

ICache.scala

icache: add a couple cover points for I$ and ITIM iteraction

2017-11-20 13:14:38 -08:00

IDecode.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

Instructions.scala

Add RVC instruction patterns

2017-07-25 15:19:16 -07:00

Multiplier.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

NBDcache.scala

tilelink: split Acquire into Acquire{Block,Perm} (#1030)

2017-10-05 12:49:49 -07:00

package.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

PMP.scala

Move microarchitecture-neutral params from Rocket to Core

2017-10-03 17:34:18 -07:00

PTW.scala

Don't emit PTW covers when !usingVM

2017-11-03 15:03:27 -07:00

RocketCore.scala

Provide option to support AMOs only on I/O, not DTIM/D$

2017-11-09 17:45:53 -08:00

RVC.scala

Expand C.UNIMP correctly (#1052)

2017-10-12 14:00:14 -07:00

ScratchpadSlavePort.scala

tile: bus blocker needs to know width :(

2017-11-17 20:17:17 -08:00

SimpleHellaCacheIF.scala

Refactor package hierarchy and remove legacy bus protocol implementations (#845)

2017-07-07 10:48:16 -07:00

TLB.scala

Provide option to support AMOs only on I/O, not DTIM/D$

2017-11-09 17:45:53 -08:00

TLBPermissions.scala

rocket: only cache when AcquireT is possible

2017-10-10 18:06:58 -07:00