a48dd575b2
Merge pull request #1254 from freechipsproject/amo-aqrl
...
Fix mapping of acquire/release AMOs to fence operations
2018-02-27 19:49:40 -06:00
86c10b3cef
Merge pull request #1250 from seldridge/add-jtag-vpi-c-vsim
...
Add jtag_vpi.c to sources for vsim
2018-02-26 15:40:12 -07:00
4bcc42550e
Remove JTAG vpi from VCS build
...
h/t @mwachs5
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com >
2018-02-26 15:12:18 -05:00
47d63d6baa
Merge pull request #1251 from freechipsproject/rocket_covers
...
Added functional covers
2018-02-25 09:01:33 -08:00
eb6e192ec0
Fix mapping of acquire/release AMOs to fence operations
...
AMO.aq should be implemented as AMO;FENCE, whereas AMO.rl should be
implemented as FENCE;AMO. These had been swapped. This error does
not affect cacheable accesses using the blocking D$, nor does it
affect accesses to the data scratchpad, nor does it affect accesses
to strongly ordered I/O regions (which is the default).
Cacheable accesses using the nonblocking D$ and accesses to weakly
ordered I/O regions may manifest memory-ordering violations. For
these accesses, the workaround is to use AMO.aqrl whenever AMO.aq
or AMO.rl had been used.
2018-02-23 16:39:47 -08:00
95294bbdcb
PatternPusher: put data at correct address when misaligned ( #1249 )
2018-02-23 15:20:56 -08:00
d0e350976a
Add jtag_vpi.c to sources for vsim
...
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com >
2018-02-23 17:31:24 -05:00
87eed645d8
Fix JTAG cover description ( #1248 )
2018-02-23 12:13:31 -08:00
2e548c9ad2
Added functional covers
2018-02-22 23:20:12 -08:00
69b48b623a
Merge pull request #1247 from freechipsproject/misa-c
...
Implement misa.C proposal
2018-02-22 22:53:49 -08:00
aad75f2285
Implement misa.C proposal
...
This proposal hasn't been adopted yet, but anything is better than the
current implementation, where clearing misa.C when the PC is misaligned
is effectively undefined.
2018-02-22 15:12:19 -08:00
c1ee31d133
Fix debug trigger point for stores
...
In Rocket, debug triggers are supposed to happen before a store
occurs, rather than after. Previously, we reported the exception
on the store's PC, but the store occurred anyway. This probably
hasn't been problematic in practice because most stores are
idempotent.
2018-02-22 14:56:57 -08:00
32c5c3c04d
Merge pull request #1245 from freechipsproject/rv32d
...
Support fLen > xLen
2018-02-21 11:05:44 -08:00
8998a97ea1
Preserve WithRV32 behavior: FLEN = 32
2018-02-20 18:28:47 -08:00
1dc1e2c099
support testing RV32D configs
2018-02-20 16:16:39 -08:00
d4fb7ad6a2
DefaultRV32Config should provide fdiv/fsqrt
...
This is a holdover from before we had built the functional unit.
2018-02-20 16:16:39 -08:00
b487448961
Add FPUParams.fLen option, decoupled from xLen
2018-02-20 16:16:39 -08:00
5e35015651
Minor Rocket fixes to support fLen != xLen
2018-02-20 16:16:39 -08:00
bd29184e11
debug: get beatBytes from pbus, not XLen
2018-02-20 16:16:39 -08:00
62f9b84439
plic: get beatBytes from pbus, not XLen
2018-02-20 16:16:39 -08:00
52e22a1dd8
clint: get beatBytes from pbus, not XLen
2018-02-20 16:16:39 -08:00
1b158d2caf
Merge pull request #1244 from freechipsproject/dtim-priority
...
Give Rocket priority over DTIM TL port
2018-02-20 14:19:21 -08:00
1bac2cbdf8
Give Rocket priority over DTIM TL port
...
The TL port can easily starve the processor, even at only 20% utilization,
because of a bad interaction with the pipeline. Giving the processor
static priority is OK in practice, since <50% of instructions are loads
and stores in typical workloads. Even if it executes 100% loads and stores,
it must eventually encounter an I$ miss, taken branch, or exception, so
even malicious code can't permanently starve the TL port.
2018-02-20 11:23:10 -08:00
db35f45bf7
Merge pull request #1242 from freechipsproject/unnamed_reg_fix
...
RegFieldDesc: fix the output produced for undescribed registers
2018-02-16 14:27:53 -08:00
135f06cefc
Clarify errors, init jtag error code to zero ( #1241 )
...
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com >
2018-02-16 13:03:51 -08:00
5affd3bec2
RegFieldDesc: fix the output produced for undescribed registers
2018-02-16 10:24:12 -08:00
cf7cd03d64
Merge pull request #1239 from freechipsproject/reduce_debug_flags
...
Reduce Debug Module "flags"
2018-02-16 08:53:41 -08:00
bb1976552f
Merge pull request #1238 from freechipsproject/error-bifurcate
...
Error: don't be an exception wrt. caching
2018-02-15 22:19:27 -08:00
d72abb7a12
Debug: revert change to how flags are named
2018-02-15 21:49:32 -08:00
dcfbdabe60
CacheCork: better document edge conditions
2018-02-15 19:14:30 -08:00
ecd069dca4
tilelink: allow FIFO caches
...
Probably not a smart thing to build, but not illegal!
2018-02-15 19:09:37 -08:00
acecc407a5
HellaCache: we do NOT really support probe below the block size!
...
If we did, you would somehow have to retain ownership of the
unprobed parts of the block, in case they happened to be dirty.
2018-02-15 19:08:43 -08:00
c34b940d9a
ElaborationArtefacts: revert unintentional change
2018-02-15 14:23:54 -08:00
e0c3b22d61
RegFieldDesc: same string used to insert/compare
2018-02-15 14:23:27 -08:00
b95f68447f
RegFieldDesc: Prevent different RegField JSONS from overwriting eachother.
2018-02-15 14:01:47 -08:00
64d3731e45
RegFieldDesc: don't put characters into names that need to be sanitized
2018-02-15 13:25:06 -08:00
197699b93a
Debug: don't need to fully populate flags array
2018-02-15 13:23:51 -08:00
fa412246b3
Error: don't be an exception wrt. caching
...
Prior to this PR, the error device was allowed to be cached by
multiple actors despite never probing any of them. This is a
pretty unusual set of properties that has caused us trouble
several times now in the past.
Let's instead put the Error device into one of two very well
established categories: a straight-up MMIO device or a tracked
memory region.
2018-02-14 23:02:55 -08:00
e2e678d53d
Merge pull request #1183 from freechipsproject/regfield_descriptions
...
more detailed RegField descriptions
2018-02-12 14:25:06 -08:00
6f70d25ef9
Merge pull request #1184 from freechipsproject/regfield_json
...
TLRegMapper: emit a JSON file describing the register fields
2018-02-12 12:00:01 -08:00
de91672e9a
RegFieldDesc: simplify the output RegFieldDesc JSON to just a list of reg fields
2018-02-12 08:32:52 -08:00
7bf0121f07
PLIC: correct some descriptions
2018-02-12 08:31:29 -08:00
08acbe1a29
RegFieldDesc: Clean up both descriptions and JSON presentations
2018-02-11 23:57:57 -08:00
5ab4204e8a
RegField: the JSON will just leave things out of type None
2018-02-11 22:51:36 -08:00
3b44f380d8
TLRegMapper: emit a JSON file describing the register fields
2018-02-11 22:51:36 -08:00
256f8ffc6b
Clint: Annotate regmap with RegFieldDesc
2018-02-11 21:33:09 -08:00
718c88a8f9
PLIC: Annotate regmap with RegFieldDescs
2018-02-11 21:05:17 -08:00
13b120fb01
Debug: Annotate regmaps with RegFieldDescs
2018-02-10 20:11:24 -08:00
7abf6e1c8a
RegMapper: Update cover props to use new RegFieldDesc objects
2018-02-10 13:17:38 -08:00
4ab1585a78
Register Field: Add a more verbose description object
...
Add versions of the RegField functions to take it in, and
update Example device to use it.
2018-02-10 13:17:18 -08:00
