Yunsup Lee
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98b830201a
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add wen signal to dasm printf
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2014-02-25 03:31:06 -08:00 |
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Yunsup Lee
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97b1841fcf
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change dcache tag bits to 7
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2014-02-22 22:53:04 -08:00 |
|
Andrew Waterman
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a09ff9fdc7
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Revert to old AUIPC definition
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2014-02-10 19:04:42 -08:00 |
|
Quan Nguyen
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f021213b1d
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Merge remote-tracking branch 'origin/master' into hwacha-port
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2014-02-06 00:21:28 -08:00 |
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Andrew Waterman
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62e9313aef
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Add 16 microarchitectural counters
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2014-02-06 00:13:02 -08:00 |
|
Yunsup Lee
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ff7cae29f7
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hookup rocc interrupt and s bit
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2014-02-06 00:09:42 -08:00 |
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Andrew Waterman
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a7489920ce
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Support CSR atomics on all CSRs, not just STATUS
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2014-01-21 16:17:39 -08:00 |
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Andrew Waterman
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e8486817e6
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Clean up formatting (i.e. remove tabs, semicolons)
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2014-01-13 21:43:56 -08:00 |
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Andrew Waterman
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4d236979bd
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Fix very far forward JALs
We were sign-extending from the wrong bit, causing a backwards jump.
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2014-01-13 00:55:48 -08:00 |
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Andrew Waterman
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da3135ac9b
|
Begin integer unit clean-up
...to make it easier to generate the superscalar version of the core.
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2013-12-09 15:06:13 -08:00 |
|
Andrew Waterman
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924261e2b2
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Update to new privileged ISA... phew
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2013-11-25 04:35:15 -08:00 |
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Andrew Waterman
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65b8340cea
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Mitigate D$ hit -> branch -> NPC critical path
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2013-11-24 14:21:03 -08:00 |
|
Yunsup Lee
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c1966e2b0a
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forgot to put htif into uncore package
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2013-11-07 15:42:03 -08:00 |
|
Andrew Waterman
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b44dafbdca
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Simplify branch offset mux
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2013-10-29 13:20:40 -07:00 |
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Andrew Waterman
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1d2f4f8437
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New ISA encoding, AUIPC semantics
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2013-09-21 06:32:40 -07:00 |
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Andrew Waterman
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88d1c47665
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don't disassemble within chisel
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2013-09-15 04:14:45 -07:00 |
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Andrew Waterman
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f12bbc1e43
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working RoCC AccumulatorExample
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2013-09-14 22:34:53 -07:00 |
|
Andrew Waterman
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18968dfbc7
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Move store data generation into cache
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2013-09-14 16:15:07 -07:00 |
|
Andrew Waterman
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a0cb711451
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Start adding RoCC
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2013-09-14 15:31:50 -07:00 |
|
Andrew Waterman
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d053bdc89f
|
Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
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2013-09-12 22:34:38 -07:00 |
|
Andrew Waterman
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243c4ae342
|
sync up rocket with new isa
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2013-09-12 03:44:38 -07:00 |
|
Andrew Waterman
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67f80ba4b2
|
Stall div/mul writeback until WB slot is free
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2013-08-24 14:44:17 -07:00 |
|
Andrew Waterman
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52e31f3298
|
Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
|
2013-08-24 14:44:04 -07:00 |
|
Andrew Waterman
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d4a0db4575
|
Reflect ISA changes
|
2013-08-24 14:43:55 -07:00 |
|
Henry Cook
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3a266cbbfa
|
final Reg changes
|
2013-08-15 15:28:15 -07:00 |
|
Henry Cook
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1a9e43aa11
|
initial attempt at upgrade
|
2013-08-12 10:39:11 -07:00 |
|
Henry Cook
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4eaab214d2
|
Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:29:51 -07:00 |
|
Henry Cook
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9abdf4e154
|
Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
|
2013-07-23 20:27:58 -07:00 |
|
Andrew Waterman
|
95c5147dc5
|
Add RISC-V instruction disassembler
|
2013-06-13 10:31:04 -07:00 |
|
Andrew Waterman
|
50ccc20bf3
|
replace RDNPC with AUIPC
|
2013-04-22 04:20:15 -07:00 |
|
Andrew Waterman
|
8cbdeb2abf
|
add LR/SC support
|
2013-04-04 17:07:09 -07:00 |
|
Andrew Waterman
|
8b439ef20d
|
only support setpcr/clearpcr of SR
the full PCR RMW support was wasted area/power
|
2013-04-04 17:07:08 -07:00 |
|
Henry Cook
|
6d2541aced
|
nTiles -> nClients in LogicalNetworkConfig
|
2013-03-20 14:12:36 -07:00 |
|
Henry Cook
|
e1225c5114
|
standardize IO naming convention
|
2013-01-07 13:41:36 -08:00 |
|
Andrew Waterman
|
78868f6075
|
add config option to trade mul/div area for speed
|
2013-01-06 03:47:17 -08:00 |
|
Andrew Waterman
|
05f19b21d0
|
merge multiplier and divider
|
2012-12-12 02:22:47 -08:00 |
|
Andrew Waterman
|
4608660f6e
|
torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
|
2012-12-04 05:57:53 -08:00 |
|
Andrew Waterman
|
9c857b83f0
|
refactor PCR file
|
2012-11-27 01:28:06 -08:00 |
|
Andrew Waterman
|
352bb464b5
|
clock gate X/M and M/W store data registers
|
2012-11-26 20:33:41 -08:00 |
|
Andrew Waterman
|
de2f28193a
|
get rid of more global constants
|
2012-11-25 04:24:25 -08:00 |
|
Andrew Waterman
|
c036cdc1ea
|
add option for 2-cycle load-use delay
|
2012-11-24 22:01:08 -08:00 |
|
Andrew Waterman
|
72f94d1141
|
fix virtual address sign extension detection
|
2012-11-20 04:06:57 -08:00 |
|
Andrew Waterman
|
29bc361d6c
|
remove global constants; disentangle hwacha a bit
|
2012-11-17 17:24:08 -08:00 |
|
Andrew Waterman
|
5a7777fe4d
|
clock gate integer datapath more aggressively
|
2012-11-17 06:48:44 -08:00 |
|
Andrew Waterman
|
8dce89703a
|
new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
|
2012-11-16 02:39:33 -08:00 |
|
Yunsup Lee
|
8764fe786a
|
refactored vector tlb
|
2012-11-06 23:53:52 -08:00 |
|
Andrew Waterman
|
4d1ca8ba3a
|
remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
|
2012-11-06 08:13:44 -08:00 |
|
Andrew Waterman
|
c5b93798fb
|
factor out more global constants
|
2012-11-05 23:52:32 -08:00 |
|
Andrew Waterman
|
5b20ed71be
|
move rd=0 check into bypass logic
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
|
2012-11-05 01:30:57 -08:00 |
|
Andrew Waterman
|
7380c9fe60
|
aggressively clock gate int and fp datapaths
|
2012-11-04 16:40:14 -08:00 |
|