4fe48f5a0a
bump chisel
2014-09-25 06:46:58 -07:00
60d90f5230
recover collectNodesIntoComp in Backends.scala
2014-09-25 06:46:50 -07:00
a53091b40f
remove collectNodesIntoComp from Backends.scala
2014-09-25 06:46:27 -07:00
1a101f8de5
don't use latches on mem ports for fpga
2014-09-25 06:46:21 -07:00
f4e6cd75ab
turn off fpu for default fpga config.
...
a larger fpga can use defaultconfig
2014-09-25 06:46:16 -07:00
fefa560017
Change addons subproject to use .addons-dont-touch directory instead of addons
...
This hides the directory name under standard invocations of ls and thus avoids confusing the user with extra directory names.
2014-09-25 06:46:06 -07:00
69d765744c
Adjustments to the build structure (see below)
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All 'addon' subprojects now have their sources aggregated into the addons subproject. This is done via a source copy (so that sbt will only rebuild sources that actually changed). To prevent caching issues the addons/src directory is CLEARED and then refilled every time addons is compiled. Thus, it is CRUCIAL NO SOURCES ARE MANUALLY ADDED TO addons/src AS THEY WILL BE WIPED BY addons/prepare. Due to sbt source caching, sbt will still be able to tell which sources have changed. (Strangely, sbt would not cache sources in extra unmanaged source directories and thus would always recompile them.) Also, cleaned up project/build.scala a bit to remove some warnings: Added import scala.language/postFixOps (so make! at the bottom no longer errors) and .toURI.toURL (as straight .toURL has been deprecated by the java standard library).
2014-09-25 06:45:21 -07:00
3b9624277a
normalize rocket-chip to reference-chip
2014-09-25 06:45:09 -07:00
7571695320
Removed broken or unfinished modules, new MemPipeIO converter
2014-09-24 15:11:24 -07:00
3e256439c9
Add abstract class Tile
2014-09-24 13:04:20 -07:00
82fe22f958
support for multiple tilelink paramerterizations in same design
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Conflicts:
src/main/scala/cache.scala
2014-09-24 11:30:40 -07:00
53b8d7b031
use new coherence methods in l2, ready to query dir logic
2014-09-20 18:01:14 -07:00
149d51d644
more coherence API cleanup
2014-09-20 16:57:13 -07:00
faed47d131
use thunk for dir info
2014-09-20 16:54:28 -07:00
f7b1e23ead
functional style on MuxBundle
2014-09-20 16:54:28 -07:00
180d3d365d
Expanded front-end to support superscalar fetch.
2014-09-17 14:24:03 -07:00
6495d0e6f7
bump rocket,uncore
2014-09-17 11:26:12 -07:00
f249da1803
update README
2014-09-17 11:25:14 -07:00
238f7761f6
update README
2014-09-17 11:23:25 -07:00
041a362943
push chisel
2014-09-17 11:12:12 -07:00
221007595b
allow BACKEND/CONFIG be environment variables
2014-09-17 11:12:08 -07:00
484648d9c7
Changed CONFIG from a recursively expanded variable to a conditionally
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assigned variable, allowing users to define CONFIG external to Makefile
2014-09-17 11:12:02 -07:00
ef2e96211c
bump chisel/hardfloat/rocket/uncore
2014-09-12 18:10:00 -07:00
09de2e2794
compute number of outstanding misses for DRAMSideLLCNull
2014-09-12 18:09:38 -07:00
8abf62fae3
add LICENSE
2014-09-12 18:06:41 -07:00
25180b71f7
add LICENSE
2014-09-12 15:36:42 -07:00
49b027db2c
forgot to add LICENSE file
2014-09-12 15:36:29 -07:00
0b51d70bd2
add LICENSE
2014-09-12 15:31:38 -07:00
e40a6fdd64
more tweaks to README
2014-09-12 10:22:00 -07:00
c57dea415c
fix markdown
2014-09-12 10:18:14 -07:00
1cfd9f5a0e
add LICENSE
2014-09-12 10:15:04 -07:00
2367b7beb5
Added logic to sbt so that, for rocketchip, it will automatically include src/main/scala sources from subdirectories into the rocketchip top-level project not already handled by formal subprojects
2014-09-12 01:08:11 -07:00
2c33852c52
final touches
2014-09-12 00:19:29 -07:00
275b72368b
add CONFIG to the name of simulator executable
2014-09-11 22:11:58 -07:00
c98afa1fea
turn off DRAMSideLLC
2014-09-11 22:10:25 -07:00
b5a64487eb
turn off DRAMSideLLC
2014-09-11 22:07:44 -07:00
f8d450b4e2
mark DRAMSideLLC as HasKnownBug
2014-09-11 22:06:03 -07:00
9dfaf5459e
bump hardfloat,riscv-tools
2014-09-11 03:08:21 -07:00
5f8bd18fac
Makefiles should be perfect
2014-09-11 02:53:46 -07:00
bb22ecc8b5
fix rocket interrupt issue
...
h/t Andrew
2014-09-11 02:52:05 -07:00
086bb02c24
check RISCV envirnoment variable
2014-09-11 02:38:21 -07:00
a999c055ed
Don't take an interrupt when EX stage PC is invalid
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It was possible to take an interrupt on the instruction in the shadow of
a short forward branch. EPC would thus get the wrong value, and so
a wrong-path instruction would be executed upon return from interrupt.
h/t Yunsup
2014-09-11 01:46:52 -07:00
02c08a156f
generate consts.vh from chisel source
2014-09-10 17:14:55 -07:00
cfecd8832d
tease out reference-chip specific stuff
2014-09-09 20:49:28 -07:00
6b6bdd2b83
decommission Slave top-level module for fpga build
2014-09-08 00:23:15 -07:00
ddfd3ce968
further generalize fpga/vlsi builds
2014-09-08 00:21:57 -07:00
3175a40509
add berkeley-hardfloat as submodule
2014-09-08 00:18:49 -07:00
1e5b2f658f
remove existing hardfloat repository
2014-09-07 23:45:47 -07:00
ae05125f29
Adjustements to top-level parameters and knobs for hwacha
2014-09-07 17:57:33 -07:00
5eb5e9eaf5
Standardize ()=>Module(...) top-level Parameters
2014-09-07 17:54:41 -07:00
