riscv/rocket-chip
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Author SHA1 Message Date
Yunsup Lee a950d526d2 add prefetch count queue 2012-03-05 12:09:41 -08:00
Yunsup Lee d4ec7ff4d9 refined vector exception interface 2012-03-03 16:11:54 -08:00
Yunsup Lee e28a551368 refactor code related to vector exceptions 
- revisied interfaces
- new instructions
 2012-03-03 15:15:00 -08:00
Yunsup Lee f9fb3978ca fix store prefetch bug, it no longer occupies an entry in the sdq 2012-03-03 15:14:59 -08:00
Yunsup Lee 54baa0713c hack fence.g.cv to support waiting the control processor 2012-03-02 02:10:26 -08:00
Yunsup Lee 1054cec087 add vec countq interface 2012-03-02 00:43:32 -08:00
Yunsup Lee 8678b3d70c clean up ioDecoupled/ioPipe interface 2012-03-01 20:48:46 -08:00
Yunsup Lee c7b01230f4 fix mul/div when waddr=0, can't believe torture didn't find this one 2012-03-01 10:15:27 -08:00
Yunsup Lee a8ef5e9e27 change NMSHR when HAVE_VEC is true 2012-03-01 01:07:47 -08:00
Yunsup Lee 6847160343 refactor arbiter priorities 2012-03-01 00:22:34 -08:00
Yunsup Lee f641b44fb8 changes after the module uniquify bug fix 2012-02-29 22:00:59 -08:00
Yunsup Lee 4939b72ba5 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-29 17:12:02 -08:00
Yunsup Lee 20d0088f66 temporary fix to match bit widths for Mem 2012-02-29 17:09:31 -08:00
Yunsup Lee 3d96a2d4f0 add fpu.dec.wen := false when HAVE_FPU is turned off 2012-02-27 14:00:58 -08:00
Yunsup Lee bfd0ae125e upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache 2012-02-26 23:46:51 -08:00
Yunsup Lee f3bb02b2ea refactored dmem arbiter 2012-02-26 17:38:08 -08:00
Yunsup Lee 766a039ffe small changes to the dtlb arbiter 2012-02-26 16:19:50 -08:00
Yunsup Lee 49efe4b744 now vu steals cycles from the fpu's fma alu 2012-02-26 01:55:07 -08:00
Yunsup Lee 94ba32bbd3 change package name and sbt project name to rocket 2012-02-25 17:09:26 -08:00
Yunsup Lee 946e0c6e4e add vector exception infrastructure 2012-02-25 16:37:56 -08:00
Yunsup Lee 3839e3a318 massive refactoring of vector constants 2012-02-25 15:55:36 -08:00
Yunsup Lee a1600d95db fix bug related to waddr and wdata in wb stage 
for the instructions which don't use waddr/wdata for writeback, the contents were getting overwritten by the ll ops
it manifested itself after cp imul were sharing the alu with the vu
 2012-02-25 12:21:10 -08:00
Yunsup Lee 137fd62007 refactor cpfences 2012-02-25 12:20:36 -08:00
Yunsup Lee 63939efd0c fix ctrl vec iface hookup - final 2012-02-23 23:03:44 -08:00
Yunsup Lee bf1e643913 fix ctrl vec iface hookup 2012-02-23 22:55:25 -08:00
Yunsup Lee 2ea309cf80 bug fixes to ctrl_vec 2012-02-23 22:35:05 -08:00
Yunsup Lee 91a0bb6f61 add vector prefetch queues 2012-02-23 22:30:38 -08:00
Yunsup Lee e53792a1eb fix bug in rocket's vector datapath related to wakeup 2012-02-23 10:14:14 -08:00
Yunsup Lee 82cd3625c2 add in vackq interface 2012-02-15 17:53:24 -08:00
Yunsup Lee 258d050e1b add stall logic for vector command queues 2012-02-15 14:48:41 -08:00
Yunsup Lee 32bdf5098a refactor vector control logic & datapath in the rocket core 2012-02-15 13:30:22 -08:00
Yunsup Lee 7c11c1406c vector-vector add working! 2012-02-15 02:28:07 -08:00
Yunsup Lee 6bdf9dc513 hwacha integration: now it compiles correctly! 2012-02-14 23:34:57 -08:00
Yunsup Lee a51c7cc927 new build system with updated chisel, hwacha 2012-02-14 19:43:59 -08:00
Yunsup Lee f47d888feb vvcfgivl and vsetvl works 2012-02-09 02:35:21 -08:00
Yunsup Lee fcc8081c4d hook up the vector command queue 2012-02-09 01:28:16 -08:00
Yunsup Lee 9285a52f25 initial vu integration 2012-02-08 21:43:45 -08:00
Yunsup Lee 0ea2704b80 new mftx instruction format 2011-12-12 03:23:12 -08:00