riscv/rocket-chip
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fix store prefetch bug, it no longer occupies an entry in the sdq

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This commit is contained in:
Yunsup Lee 2012-03-03 15:07:22 -08:00
parent 1b3307df32
commit f9fb3978ca
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/coherence.scala
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@ -92,8 +92,8 @@ object cpuCmdToRW {
val store = (cmd === M_XWR)
val load = (cmd === M_XRD)
val amo = cmd(3).toBool
val read = load || amo || (cmd === M_PFR)
val write = store || amo || (cmd === M_PFW)
val read = load || amo || (cmd === M_PFR) || (cmd === M_PFW)
val write = store || amo
(read, write)
}
}