Henry Cook
8ff6e21e3a
Fixed race between read resps/reps and write req/reps in null hub
2012-02-29 00:44:03 -08:00
Andrew Waterman
c99f6bbeb7
separate memory request command and data
...
also, merge some VLSI/C++ test harness functionality
2012-02-28 19:06:23 -08:00
Henry Cook
040aa9fe02
Added temporary ioMemHub and made coherence hub implementations depend on it rather than ioMem
2012-02-28 17:33:32 -08:00
Daiwei Li
3f998b1353
send vcfg and setvl to vu prefetch queues
2012-02-28 14:54:48 -08:00
Henry Cook
5cc10337b4
Null coherence hub. Begin work on internal tracker logic
2012-02-27 19:10:15 -08:00
Andrew Waterman
2b1c07c723
replace ioDCache with ioMem
2012-02-27 18:36:09 -08:00
Andrew Waterman
1d41a41afa
remove extraneous constants
2012-02-27 17:49:48 -08:00
Yunsup Lee
3d96a2d4f0
add fpu.dec.wen := false when HAVE_FPU is turned off
2012-02-27 14:00:58 -08:00
Henry Cook
f0588a0052
Added probe_req ready sigs, GenArray to Vec
2012-02-27 11:26:18 -08:00
Henry Cook
7a8f53a117
probe req transactors in coherence hub
2012-02-27 09:24:33 -08:00
Henry Cook
2275239f33
xact init transactors in coherence hub
2012-02-27 09:24:32 -08:00
Yunsup Lee
bfd0ae125e
upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache
2012-02-26 23:46:51 -08:00
Andrew Waterman
6e706c7c74
fix yet another AMO-related replay bug
2012-02-26 20:20:45 -08:00
Andrew Waterman
e12b9eae93
remove ext_mem interface
...
hindsight is 20/20
2012-02-26 18:53:39 -08:00
Andrew Waterman
2d04664a98
simplify cpu-cache interface
2012-02-26 18:26:29 -08:00
Andrew Waterman
ad713a5d83
fix icache ram depth; new chisel
2012-02-26 17:51:46 -08:00
Yunsup Lee
f3bb02b2ea
refactored dmem arbiter
2012-02-26 17:38:08 -08:00
Huy Vo
93f41d3359
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-02-26 17:24:23 -08:00
Huy Vo
5b0f7ccf68
updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
2012-02-26 17:24:08 -08:00
Yunsup Lee
766a039ffe
small changes to the dtlb arbiter
2012-02-26 16:19:50 -08:00
Daiwei Li
69260756bd
change ppn and vpn in dtlb from ufix to bits
2012-02-26 02:54:31 -08:00
Yunsup Lee
49efe4b744
now vu steals cycles from the fpu's fma alu
2012-02-26 01:55:07 -08:00
Daiwei Li
47dbc2a417
head should be working again
2012-02-26 00:30:50 -08:00
Daiwei Li
569698b824
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-25 22:05:30 -08:00
Yunsup Lee
94ba32bbd3
change package name and sbt project name to rocket
2012-02-25 17:09:26 -08:00
Yunsup Lee
946e0c6e4e
add vector exception infrastructure
2012-02-25 16:37:56 -08:00
Yunsup Lee
3839e3a318
massive refactoring of vector constants
2012-02-25 15:55:36 -08:00
Henry Cook
3980120279
More stylish bundle param names, some hub progress
2012-02-25 15:27:53 -08:00
Henry Cook
db6d480778
Better foldR
2012-02-25 15:27:09 -08:00
Henry Cook
df97de0fd3
Better abstraction of data bundles
2012-02-25 12:57:01 -08:00
Henry Cook
4fa31b300b
Added popcount util
2012-02-25 12:57:01 -08:00
Yunsup Lee
a1600d95db
fix bug related to waddr and wdata in wb stage
...
for the instructions which don't use waddr/wdata for writeback, the contents were getting overwritten by the ll ops
it manifested itself after cp imul were sharing the alu with the vu
2012-02-25 12:21:10 -08:00
Yunsup Lee
137fd62007
refactor cpfences
2012-02-25 12:20:36 -08:00
Andrew Waterman
4121fb178c
clean up mul/div interface; use VU mul if HAVE_VEC
2012-02-24 19:22:35 -08:00
Andrew Waterman
b3a3289d34
fix (?) external memory request nack interface
2012-02-24 01:42:33 -08:00
Daiwei Li
477f3cde02
added prefetch queues for vu
2012-02-24 00:44:13 -08:00
Yunsup Lee
63939efd0c
fix ctrl vec iface hookup - final
2012-02-23 23:03:44 -08:00
Yunsup Lee
bf1e643913
fix ctrl vec iface hookup
2012-02-23 22:55:25 -08:00
Andrew Waterman
7b3cce79e3
allocate a primary miss on a prefetch
2012-02-23 22:40:24 -08:00
Yunsup Lee
2ea309cf80
bug fixes to ctrl_vec
2012-02-23 22:35:05 -08:00
Yunsup Lee
91a0bb6f61
add vector prefetch queues
2012-02-23 22:30:38 -08:00
Andrew Waterman
012028efaa
fix fpga build
2012-02-23 22:19:38 -08:00
Henry Cook
52da831aa3
finished xact_finish and xact_abort transactors in coherence hub
2012-02-23 18:12:50 -08:00
Henry Cook
1c1ce7d60b
finished xact_rep transactor in coherence hub
2012-02-23 17:50:02 -08:00
Andrew Waterman
5332bab6f1
expose FMA ports outside of FPU (for the VU)
2012-02-23 17:39:34 -08:00
Andrew Waterman
6ceaa0e80a
correct and simplify replay_next logic
2012-02-23 16:52:52 -08:00
Andrew Waterman
f939088be1
move datapath control signals into control unit
...
because that's where control signals go
2012-02-23 16:52:52 -08:00
Yunsup Lee
e53792a1eb
fix bug in rocket's vector datapath related to wakeup
2012-02-23 10:14:14 -08:00
Andrew Waterman
7c929afe2b
HTIF now controls CPU reset
2012-02-22 19:30:03 -08:00
Andrew Waterman
3eebf40310
nack CPU requests during any replay
2012-02-22 18:37:13 -08:00