3cbc5262ec
Don't permit new acquires until the release queue is drained
...
If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.
2017-08-13 13:18:45 -07:00
0190724492
Actually use the C-channel acquire-before-release queue
...
oops...
2017-08-13 13:03:35 -07:00
7387f2a93a
Don't block D-channel when handling a probe
...
This is an acquire-before-release regression.
2017-08-12 16:13:24 -07:00
604abd5b07
Only report ECC errors when the RAM was actually read
2017-08-12 15:28:03 -07:00
18fb052fc9
DRY
2017-08-12 15:27:30 -07:00
176110b6d3
Don't trigger ECC writebacks when a release is in flight
2017-08-12 15:23:57 -07:00
0a591c5b5b
Roll back use of UIntToOH1 ( #946 )
...
These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass. This is not yet conclusive.
2017-08-09 18:39:47 -07:00
721770244e
Fix IBuf bug
...
Don't examine a packet's xcpt signal if it might be invalid. In this case,
the correct fix is to not examine xcpt at all; the deleted code was vestigial.
(Note, the other use of xcpt(j+1) in this code is indeed safe.)
2017-08-09 09:47:51 -07:00
809c7e8551
Don't merge stores that manifest WAW hazards
...
The following sequence would drop the first store when eccBytes=4:
sb x0, 0(t0)
nop
sb x0, 4(t0)
nop
sb x0, 1(t0)
Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.
2017-08-08 15:19:05 -07:00
82e13443b2
Merge pull request #937 from freechipsproject/critical-paths
...
Perform tag error detectoin/correction in same cycle as RAM
2017-08-08 15:03:28 -07:00
7935c61c19
Don't report to the DTIM that data is cacheable
...
Otherwise, it will attempt to perform AMOs where they're unsupported!
2017-08-08 11:55:04 -07:00
74d309c18e
Make I vs. D a static property of TLB, not an input pin
...
The microarchitecture doesn't really support unified TLBs, so don't fake it.
2017-08-08 11:54:47 -07:00
e92981b0bd
DRY
2017-08-08 11:46:38 -07:00
62ccba304c
Perform tag error detectoin/correction in same cycle as RAM
...
The tag RAMs tend to be fast, so take up some of the slack.
This makes s2_nack faster.
2017-08-08 10:21:30 -07:00
6d1d285464
Merge pull request #933 from freechipsproject/cinst
...
Print out the compressed instruction when executing one
2017-08-07 21:40:10 -07:00
402907990c
Revert "Remove one gate from D$ ECC check"
...
This reverts commit 7d94074b05
2017-08-07 17:33:20 -07:00
fc0d5fcf98
Print out the compressed instruction when executing one
2017-08-07 17:21:53 -07:00
658e36f98b
Reduce fanout on frontend io.cpu.req.valid signal
2017-08-06 17:38:51 -07:00
7d94074b05
Remove one gate from D$ ECC check
...
The D$ corrects via writeback, so which word the error was in doesn't
matter, as the entire line is corrected.
2017-08-06 17:36:53 -07:00
83875e3a0c
Only flush D$ on FENCE.I if it won't always be probed on I$ miss
2017-08-05 14:22:40 -07:00
991e16de92
Remove probe address mux from TLB response path
2017-08-05 12:57:38 -07:00
b9b4142bb4
Get s2_nack off the critical path
...
We were using it to compute the next PC on flush vs. replay (which require
PC+4 and PC, respectively). This fix gets rid of the adder altogether by
reusing the M-stage PC in the flush case, which by construction holds PC+4.
2017-08-05 00:30:36 -07:00
6112adfbb0
Get L2 TLB tag/parity check off the D$ arbitration path
2017-08-04 17:01:51 -07:00
8d97684555
Fix L2 TLB perfctr
...
It was counting conflict misses but not cold misses.
2017-08-04 17:01:31 -07:00
df7f09b9ce
Get I$ ECC check further off critical path
2017-08-04 16:59:21 -07:00
4bfbe75d74
Avoid pipeline replays when fetch queue is full
2017-08-04 16:59:21 -07:00
a45997d03f
Separate I$ parity error from miss signal
...
Handle parity errors with a pipeline flush rather than a faster
frontend replay, reducing a critical path.
2017-08-04 16:59:21 -07:00
06a831310b
Shave a gate delay off I$ backpressure path
...
The deleted code was a holdover from Hwacha's vector fences.
2017-08-04 13:12:43 -07:00
ecc2ee366c
Shave a few gate delays off IBuf control logic
...
It takes a while for the pipeline to compute the stall signal, so avoid
using it until the last logic levels in the clock cycle.
2017-08-04 13:12:43 -07:00
7937db0c84
Merge pull request #919 from freechipsproject/imiss-perf-counter
...
Fix I$ miss perfctr
2017-08-04 01:04:23 -07:00
ba4eecc0f0
Use UIntToOH1 ( #921 )
...
Closes #920
2017-08-03 14:55:39 -07:00
f483bab4aa
Fix I$ miss perfctr
...
The old version was counting prefetches, too.
2017-08-03 00:52:12 -07:00
1be1433f04
Merge pull request #918 from freechipsproject/icache-prefetch
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Icache prefetch
2017-08-02 21:22:20 -07:00
2537d0d54e
Optionally prefetch next I$ line into L2$ on miss
2017-08-02 17:10:56 -07:00
744cdb2f72
Make TLB report when it's safe to prefetch within a page
2017-08-02 17:09:38 -07:00
7d2dd3769f
Optimize a hazard check critical path
2017-08-02 14:27:25 -07:00
2eb239d03f
Add option to retime D$ way mux into subsequent pipeline stage
2017-08-01 23:59:20 -07:00
9464c6db40
Mitigate(?) frontend critical path
2017-08-01 18:51:17 -07:00
735701382f
Mitigate some I$ response valid critical paths
2017-08-01 18:51:17 -07:00
2ecea2ef60
Don't use a pipe queue on D$ TL A-channel
...
This cuts an I$->D$ path.
2017-08-01 15:17:07 -07:00
5681693ccc
Fix a D$ ready-valid signaling regression
...
I broke this in 66d06460fa
2017-07-31 18:05:14 -07:00
7adfd5c431
Merge pull request #906 from freechipsproject/critical-paths
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Mitigate I$->D$->I$ critical path
2017-07-31 16:14:11 -07:00
11332c1226
dcache: break potential combinatorial loop by making pstore_drain_on_miss more conservative
2017-07-31 14:03:30 -07:00
d811692c3b
Mitigate I$->D$->I$ critical path
...
This seemingly irrelevant change shaves several gate delays off the I$
tl.a.valid path.
2017-07-31 01:43:04 -07:00
ac4339a8e7
Pass D$ backpressure to D-channel, rather than asserting
2017-07-29 11:48:36 -07:00
edcd2c696c
Avoid needless stall on E-channel back pressure
2017-07-29 11:47:58 -07:00
fdb8935712
Improve fidelity of two perf counters
2017-07-28 13:14:04 -07:00
4c82f6b77e
Don't refill BTB on not-taken branches
2017-07-28 13:13:52 -07:00
2e8b02e780
Merge D$ store hits when ECC is enabled
...
This avoids pipeline flushes due to subword WAW hazards, as with
consecutive byte stores.
2017-07-28 12:56:36 -07:00
838864870e
Bypass TLB refill signal to halve L2 TLB hit time
...
The 4-cycle hit time is 1 cycle too long to avoid a second
pipeline replay, so it was effectively 9 cycles instead of 4.
2017-07-28 12:56:36 -07:00
ae1f7a95f6
Don't nack misses when there's a pending store
...
That effectively increased the miss latency by 5 cycles when there was
a store hit followed by a load miss. Since pending stores are drained
when releaseInFlight, the check I removed was redundant.
2017-07-28 12:56:36 -07:00
9804bdc34e
tilelink: remove obsolete addr_lo signal ( #895 )
...
When we first implemented TL, we thought this was helpful, because
it made WidthWidgets stateless in all cases. However, it put too
much burden on all other masters and slaves, none of which benefitted
from this signal. Furthermore, even with addr_lo, WidthWidgets were
information lossy because when they widen, they have no information
about what to fill in the new high bits of addr_lo.
2017-07-26 16:01:21 -07:00
5a5b78b15e
Improve L2 TLB coding style
2017-07-26 02:22:43 -07:00
5a9c673f41
Fix L2 TLB response bug
...
Sometimes, it would inform the L1 TLB that the translation was for
a superpage, even though that's never the case.
2017-07-26 02:20:41 -07:00
acca0fccf5
Fix BTB not being refilled on some indirect jumps
...
We are overloading the BTB-hit signal to mean that any part of the frontend
changed the control-flow, not just the BTB. That's the right thing to do for
most of the control logic, but it means the BTB sometimes won't get refilled
when we'd like it to. This commit makes the frontend use an invalid BTB entry
number when it, rather than the BTB, changes the control flow. Since the
entry number is invalid, the BTB will treat it as a miss and refill itself.
This is kind of a hack, but a more palatable fix requires reworking the RVC
IBuf, which I don't have time for right now.
2017-07-26 02:13:43 -07:00
15878d4691
Perform some control-flow transfers within the Frontend
2017-07-25 15:19:16 -07:00
62c4080585
Add RVC instruction patterns
2017-07-25 15:19:16 -07:00
66d06460fa
Add option for acquire-before-release
2017-07-25 15:19:16 -07:00
86ccd935fc
Add method to print perf events
2017-07-25 15:19:16 -07:00
5df8f0d1ea
Add L2 TLB miss counter
2017-07-25 15:19:16 -07:00
01ca3efc2b
Combine Coreplex and System Module Hierarchies ( #875 )
...
* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
4eface8a9e
rocket: do not require FIFO order for memory-like regions
2017-07-12 17:39:00 -07:00
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
...
* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
a0cbc376b4
Merge pull request #849 from freechipsproject/l2-tlb
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L1 memory system improvements
2017-07-06 13:03:06 -07:00
e1cc0a0a0e
Mask debug interrupts similarly to other interrupts ( #847 )
...
This makes single-step exceptions higher-priority than debug interrupts.
2017-07-06 12:03:24 -07:00
b2351c5fbf
Use consistent casing
2017-07-06 11:16:56 -07:00
be4eceec0d
Fix stupid D$ probe bug
2017-07-06 01:20:47 -07:00
90a7d6a343
Add L2 TLB option
2017-07-06 01:19:18 -07:00
438abc76d2
Handle TL errors in L1 I$
...
Cache the error bit in the tag array; report precisely on access.
2017-07-06 01:02:11 -07:00
0ef45fac9b
Add tag ECC to D$
2017-07-03 18:16:37 -07:00
e9752f76ae
Improve probe state machine
...
- Reduce reliance on s2_prb_ack_data due to future ECC changes
- Shave a cycle off valid, but clean, probes
- Code cleanup
2017-07-03 16:25:04 -07:00
5b46350bc3
Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment.
2017-06-30 17:44:16 -07:00
5edc4546e3
rocket: add dtim and itim refs to cpus
2017-06-28 23:10:58 -07:00
7d6f8d48f2
Revert "rocket: link dtim to its cpu"
...
This reverts commit e6c2d446cc
2017-06-28 23:10:57 -07:00
fbcd6f0eb2
Revert "rocket: link itim to its cpu"
...
This reverts commit 48390ed604
2017-06-28 23:10:57 -07:00
6e5a4c687f
diplomacy: a type of connect that always disables monitors ( #828 )
2017-06-28 21:48:10 -07:00
992b480c74
Merge pull request #825 from freechipsproject/debug_wfi
...
Debug + WFI Interactions
2017-06-28 21:28:51 -07:00
ca3030cba3
dcache: fix a gender inversion bug introduced in #826
2017-06-28 15:38:53 -07:00
48390ed604
rocket: link itim to its cpu
2017-06-28 15:06:19 -07:00
e6c2d446cc
rocket: link dtim to its cpu
2017-06-28 15:06:19 -07:00
3f6d5110cd
rocket: dtim is not a dcache
2017-06-28 15:06:19 -07:00
84dc23c215
devices: add reg-names to most devices
2017-06-28 15:06:16 -07:00
852f03282f
rocket: give itim and dtim a compatible field for drivers to match
2017-06-28 14:26:55 -07:00
b9a934ae28
Support eccBytes > 1
2017-06-28 02:09:18 -07:00
8e4be40efc
Propagate wb_reg_rs2 for sfence ASID
...
This would have been a bug if we supported ASIDs.
2017-06-28 02:09:18 -07:00
2077e4190b
Make log more sensible for long-latency operations
...
Show only one write to the destination register, not two.
2017-06-28 02:09:18 -07:00
6f8fdff762
Basic L1 D$ ECC support
...
Only supports ECC on data, not tags; only supports byte granularity.
2017-06-28 02:09:18 -07:00
6100600179
Minor D$ code cleanup
2017-06-28 02:09:18 -07:00
3e04a99f61
Refactor frontend exception passing
...
Bundle them, and leverage regularity, so that if we have to add more
exceptions in the future, we don't need to change so much code.
2017-06-28 02:09:18 -07:00
cc2f87c214
Forbid S-mode execution from user memory
...
285c81746f
2017-06-28 02:09:18 -07:00
8aa16a11f3
Reduce D$ access energy when refill width > access width
2017-06-28 02:09:18 -07:00
25f585f2a9
Remove unused signal from TLB interface
2017-06-28 02:09:18 -07:00
d5f80df0ae
Allow speculative I$ refill to cacheable regions
...
Backpedaling on 27b143013f
2017-06-28 02:09:18 -07:00
e1fe0f245b
debug: Don't reset debugint register, as none of the interrupt registers are.
2017-06-27 14:10:13 -07:00
136e4b6c27
debug: use consistent coding style (Reg(init ... ) vs RegInit)
2017-06-27 13:42:38 -07:00
3b9550ede3
debug: correctly declare reg_debugint
2017-06-27 13:42:38 -07:00
56839b2c62
debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec)
2017-06-27 13:42:38 -07:00
665c2a349c
Correct Debug + WFI Interactions
...
1) Debug interrupt should end WFI
2) WFI should end immedately during single-step
3) WFI should act like NOP during Debug Mode
2017-06-27 13:42:38 -07:00
c9cfe46604
rocket,Rocket: fix type mismatch ( #819 )
2017-06-27 11:22:08 -07:00
aced18b3bb
Move RoCC interface to Diplomacy and TL2 ( #807 )
...
* Move RoCC interface to Diplomacy and TL2
* guard rocc arbiter to prevent zero-width wires
2017-06-22 12:07:09 -07:00
5552f23294
tims: explictly name them for generated address map
2017-06-20 17:18:29 -07:00
6b79842e66
dcache: just left shift by untagbits to get tag
...
Always safe because of the requirement on coreplex/RocketTiles.scala:126
2017-06-20 16:35:28 -07:00
f396b4142d
Merge pull request #806 from freechipsproject/mulh
...
Improve integer mul/div
2017-06-20 13:01:16 -07:00
675f183dd2
refactor ICache to be reusable by other frontends ( #808 )
...
* refactor ICache to be reusable by other frontends
specifically one that would like to change the fetch width and number of
bytes in an instruction
2017-06-20 08:21:01 -07:00
a6d9884cc0
Improve integer mul/div
...
- Signed integer multiplication latency is now deterministic (before,
it would take an extra cycle if the multiplier was negative).
- High-part multiplication is now one cycle faster.
- RV64 MULW now takes half as many cycles as MUL.
- Positive remainders are now one cycle faster.
2017-06-19 12:09:21 -07:00
61c39da475
Check for rvc before declaring illegal instruction after an ebreak.
2017-06-16 10:49:36 -07:00
8552c77972
Fix I$ reset regression FU-357
...
Can't rely on s2 TLB response, so mask using s2_valid.
2017-06-09 00:48:24 -07:00
16ecbdd5b2
Reduce fanout on critical I$ miss signal
2017-06-02 20:45:50 -07:00
27b143013f
Improve ITLB QoR
...
- No need to check cacheability
- Remove a gate delay from PMP path
2017-06-02 20:45:50 -07:00
80c63c0da6
rocket: include hartid in cache master names
2017-06-02 15:52:23 -07:00
d25ad10592
diplomacy: require masters to have a name
2017-06-02 15:52:20 -07:00
0fe625c52f
diplomacy: improve PMA circuit QoR
2017-06-01 15:30:20 -07:00
e3e77d68e6
PTW now does not require atomic memory operations, so take out the requirement ( #767 )
...
Bug fix in CSR which manifest itself when compiling a config with no extension
2017-05-26 13:11:15 -07:00
dbc5e7c494
Add TLB miss performance counters ( #762 )
2017-05-23 12:52:25 -07:00
b2b4c1abcd
Separate tag ECC and data ECC options ( #761 )
2017-05-23 12:51:48 -07:00
a19fc2549e
tile: add tileBus xbar
2017-05-16 16:12:01 -07:00
18725a05b0
DTS tweaks ( #740 )
...
* rocket: do not report 's' in isa string
* rocket: report the micro-architecture of the core
2017-05-12 05:32:57 -07:00
7eefc12705
Support vectored stvec interrupts, too
...
137812654e
2017-05-07 15:40:08 -07:00
c6135a02df
Revert "rocket: hard-wire UXL/SXL fields to 0"
...
This reverts commit ea0714bfcb326bec83de
2017-05-07 15:23:21 -07:00
dd1546fd69
Check PPN LSBs for superpage PTEs
...
5a32fe8782
2017-05-05 15:30:09 -07:00
1b3b228790
ITIM supports PutPartial
2017-05-04 00:57:52 -07:00
398600d4da
Interlock to prevent ITIM hazard when tl.a.valid & tl.d.valid & !tl.d.ready
2017-05-04 00:57:29 -07:00
fa6ecdf813
Fix RVC/uncacheable instruction memory performance bug
...
9c1d126965
2017-05-03 17:52:06 -07:00
f8c92d2669
Merge branch 'master' into pipeline-mmio
2017-05-03 08:37:12 -07:00
4efcb5a139
Increase frontend decoupling ( #722 )
...
Reduce pathological RVC stalls
2017-05-03 07:54:46 -07:00
4dd3345db2
Merge branch 'master' into pipeline-mmio
2017-05-02 16:23:26 -07:00
3a1a37d41b
Support PutPartial in ScratchpadSlavePort
2017-05-02 03:07:02 -07:00
f8151ce786
Remove subword load muxing in ScratchpadSlavePort
2017-05-02 00:14:46 -07:00
f49172b5bc
ScratchpadSlavePort doesn't support byte/halfword atomics
2017-05-02 00:14:46 -07:00
3d06f01a2c
rocket: turn on early ack for ITIM
2017-05-01 22:53:41 -07:00
30f1f1e7c7
rocket: turn on early ack for DTIM
2017-05-01 22:53:41 -07:00
d6e69066a5
Fix ITIM loads ( #716 )
...
An incorrectly-set ready signal caused bad data to be read from the RAM.
2017-05-01 17:41:25 -07:00
dd85d7e0a0
I$: Don't raise io.resp.valid if io.s1_kill was high previous cycle
...
@solomatnikov found the bug. It doesn't manifest in Rocket because the
Frontend masks io.resp.valid with s2_valid.
2017-04-28 16:44:58 -07:00
d67738204f
Interrupts: Less Pessimistic Synchronization ( #714 )
...
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.
* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC
* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.
* interrupts: use consistent async/periph/core ordering
* interrupts: Properly condition on 0 External interrupts
* interrupts: CLINT is also synchronous to periph clock
2017-04-28 14:49:24 -07:00
7416f2a17e
Unbreak groundtest
2017-04-28 02:10:33 -07:00
8fd5ecdff8
Set io.cpu.resp.bits.addr for MMIO loads without affecting QoR
2017-04-27 19:50:38 -07:00
3d0ed80ef6
new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels
2017-04-27 18:17:31 -07:00
99de42d34c
Swap order of ITIM WidthWidget and Fragmenter
...
e99fa057ac
2017-04-27 15:30:02 -07:00
8c10caeef9
Express PMP mask generation with incrementer, not adder
...
DC apparently doesn't always pick up the ((x + 1) ^ x) idiom.
Use (x + ~(x + 1)) instead.
2017-04-27 15:16:29 -07:00
e99fa057ac
cleanup scratchpad nodes
2017-04-27 14:02:05 -07:00
b2b4725522
Fix zero-width wire issues when ITIM is disabled
2017-04-26 22:43:00 -07:00
e23ee274f6
Size hartid field with NTiles, not XLen
2017-04-26 20:11:43 -07:00
dc753bfa95
Fix I$ elaboration when ITIM is disabled
2017-04-26 19:35:35 -07:00
80d826b94a
Make DTIM deduplicatable
2017-04-26 19:35:35 -07:00
418879a47f
Add Instruction Tightly Integrated Memory
2017-04-26 19:35:35 -07:00
f3ab23d068
dcache: fix stupidly wrong crossing comparison ( #703 )
2017-04-25 09:18:41 -07:00
4807ce7ced
dcache: put a flow Q to absorb back-pressure without restarting pipeline ( #701 )
...
* dcache: put a flow Q to absorb back-pressure without restarting pipeline
When used with a RationalCrossing, pipelined MMIO does not come out cleanly.
The first beat works, but if the second beat gets stalled, the pipeline is
restarted. This is a quick hacky test to absorb the beats. Perhaps a better
fix can be made to achieve the same effect.
* dcache: provision as few stages as possible
2017-04-24 23:28:04 -07:00
9c1d126965
Allow speculative fetch to uncacheable memory if it hits in I$ ( #700 )
...
@aswaterman it's in
2017-04-24 19:12:37 -07:00
65928dc6a0
Don't push RAS for "auipc ra, X; jalr ra, ra, Y"
2017-04-24 02:01:15 -07:00
36a7971975
Bypass scoreboard to reduce MMIO latency
2017-04-24 02:01:15 -07:00
f2d4cb8152
Update RAS speculatively from fetch stage
2017-04-24 02:01:15 -07:00
c36c171202
Use correct interrupt priority order
2017-04-24 02:01:15 -07:00
bf861293d9
Add ShiftQueue; use it
2017-04-24 02:01:15 -07:00
d24d8ff84b
Don't stall the frontend, making it easier to add more features later
2017-04-24 02:01:15 -07:00
061a0adceb
Fetch smaller parcels from the I$
2017-04-24 02:01:15 -07:00
c72b15f2a0
Down with any require() statement that makes me RTFC
2017-04-21 15:44:42 -07:00
67404a665b
When not using a cache, LR/SC isn't legal even on cacheable memory
2017-04-20 08:47:03 -07:00
d82a0dc231
Mitigate D$ exception critical path, yet again
2017-04-18 00:47:58 -07:00
c99ce7ce5d
Only report D$ exceptions on not-nacked accesses
2017-04-18 00:47:58 -07:00
a956b78dd2
In TLBPermissions, merge across some region types
...
We only care whether they have side effects or not.
2017-04-18 00:47:58 -07:00
6de6f38894
Pipeline D$ exception response into s2
2017-04-18 00:47:58 -07:00
cc9ec1d51a
Send D$ grant acks early; accept release acks early
...
We now need to block the B-channel for a few cycles after a grant to
allow the processor to get at least one request through, preventing
livelock.
2017-04-18 00:47:58 -07:00
728569c717
Reduce access-exception generation critical path
2017-04-18 00:47:58 -07:00
c366007a0d
Tighten PMAs for LR/SC and misaligned accesses
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- LR/SC on cacheable memory only (not even scratchpad)
- No misaligned accesses on regions with get/put-effects
2017-04-18 00:47:58 -07:00
74a7838de0
In TLBPermissions, don't merge regions of different types
2017-04-18 00:47:58 -07:00
7871ec82c4
Guarantee probe forward progress during LR storm
2017-04-18 00:47:58 -07:00
debcbca7de
Make PMP tolerant to PA size << VA size
2017-04-17 10:28:33 -07:00
a454edaaf7
Treat exceptions as steps for the purposes of single-stepping
2017-04-17 10:28:33 -07:00
2f22fca615
rocket: reverse input edge for better output
2017-04-14 18:09:14 -07:00
fdfcffb0b2
Catch bad physical address MSBs when VA size > PA size
2017-04-14 01:03:11 -07:00
6fbbccca3e
Improve Seq indexing QoR
2017-04-14 01:03:11 -07:00
d203c4c654
Check AMO operation legality in TLB
2017-04-14 01:03:11 -07:00
6359ff96e5
Several ScratchpadSlavePort bug fixes ( #676 )
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* only replicate scratch slave d-channel resp when AMO req
* dtim: port can't support put partial mask with holes
* dtim: use \!isRead instead of isAMO
* Fix ScratchpadSlavePort looking at wrong Acquire message
Rename acq to a in the helper method.
Delete isRead and isWrite altogether.
2017-04-13 23:25:51 -07:00
b9e042d2bf
Unconditionally write badaddr, possibly to zero
...
59d33f6b83
2017-04-12 13:35:02 -07:00
470c6711a7
Do some CSE by hand, per @terpstra
2017-04-10 22:38:25 -07:00
a43bf2feae
Add vectored interrupt support
...
4dcaa944baba6d88466a
2017-04-08 00:29:45 -07:00
c861c4925e
Don't signal access exceptions on invalid PTEs
...
The PPN should not be interpreted in this case.
2017-04-05 21:46:55 -07:00
2e09253d26
Revive I$ parity option
...
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
2017-04-05 21:46:55 -07:00
43917dd59f
Get I$ s1_kill signal off the critical path
2017-04-05 21:46:55 -07:00
744fb2e4b9
Cut imem.resp.ready critical path with a flow queue
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This is only necessary for RVC, where the decode latency is much higher.
2017-04-05 21:46:55 -07:00
3e72f9779f
Handle single-step with a pipeline stall, not a flush
...
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
2017-04-05 19:52:44 -07:00
127f121ef2
Preserve id_do_fence ( #651 )
2017-04-05 08:29:45 -07:00
19f0ae64a0
Only set id_reg_fence when AMO/FENCE is actually executed
...
This is a performance bug, not a correctness bug. But randomly stalling
because of garbage bits coming out of the I$ should be avoided.
h/t @solomatnikov
2017-04-03 21:13:52 -07:00
410e9cf736
I$ bugfix, to be reworked
2017-03-31 12:17:41 -07:00
b9550e8523
Merge branch 'master' into name-rams
2017-03-30 17:36:01 -07:00
a8a2ee711c
Give I$ RAMs consistent names
2017-03-30 15:50:54 -07:00
2720095b8e
Give D$ RAMs consistent names
2017-03-30 15:49:14 -07:00
70e7e90c02
Remove splitMetadata option from L1 caches
...
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
2017-03-30 15:48:55 -07:00
9de06f8c83
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-30 08:01:11 -07:00
fd39eadcd6
New PMP encoding
2017-03-30 00:36:23 -07:00
2f2b472098
rocket: split the interrupt controller into its own node
2017-03-30 00:36:23 -07:00
3546c8d133
If any PMPs are supported, all CSRs exist
2017-03-30 00:36:23 -07:00
8f73a58d90
Report access exception, not page fault, if page-table walk fails
2017-03-30 00:36:23 -07:00
25232070ec
Don't redundantly set resp_ae in PTW
2017-03-30 00:36:23 -07:00
d3bc99e253
get local interrupts out of the tile
2017-03-30 00:36:23 -07:00
0b9fc94421
Assertion for back-to-back uncached and cached ops ( #631 )
2017-03-29 23:07:17 -07:00
d8033b20fc
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-29 14:58:04 -07:00
44fb3be7d0
Fix MMIO/cache refill concurrency bug in DCache
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There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
2017-03-28 17:16:29 -07:00
4215f480ef
Write instruction to badaddr on illegal instruction traps
2017-03-28 00:56:14 -07:00
bb64c92906
csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again.
2017-03-27 21:21:48 -07:00
Andrew Waterman
Andrew Waterman
Palmer Dabbelt
Yunsup Lee
Henry Cook
Wesley W. Terpstra
Richard Xia
Megan Wachs
Zihao Yu
Colin Schmidt
Jacob Chang
Scott Johnson
solomatnikov