.. |
ALU.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
AMOALU.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
Breakpoint.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
BTB.scala
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Fix BTB not being refilled on some indirect jumps
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2017-07-26 02:13:43 -07:00 |
Consts.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
CSR.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
DCache.scala
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Only report ECC errors when the RAM was actually read
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2017-08-12 15:28:03 -07:00 |
Decode.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
Events.scala
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Add method to print perf events
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2017-07-25 15:19:16 -07:00 |
Frontend.scala
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Make I vs. D a static property of TLB, not an input pin
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2017-08-08 11:54:47 -07:00 |
HellaCache.scala
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Add option to retime D$ way mux into subsequent pipeline stage
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2017-08-01 23:59:20 -07:00 |
HellaCacheArbiter.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
IBuf.scala
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Roll back use of UIntToOH1 (#946)
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2017-08-09 18:39:47 -07:00 |
ICache.scala
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Separate I$ parity error from miss signal
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2017-08-04 16:59:21 -07:00 |
IDecode.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
Instructions.scala
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Add RVC instruction patterns
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2017-07-25 15:19:16 -07:00 |
Multiplier.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
NBDcache.scala
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Make I vs. D a static property of TLB, not an input pin
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2017-08-08 11:54:47 -07:00 |
package.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
PMP.scala
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Use UIntToOH1 (#921)
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2017-08-03 14:55:39 -07:00 |
PTW.scala
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Get L2 TLB tag/parity check off the D$ arbitration path
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2017-08-04 17:01:51 -07:00 |
RocketCore.scala
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Print out the compressed instruction when executing one
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2017-08-07 17:21:53 -07:00 |
RVC.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
ScratchpadSlavePort.scala
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tilelink: remove obsolete addr_lo signal (#895)
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2017-07-26 16:01:21 -07:00 |
SimpleHellaCacheIF.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |
TLB.scala
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Don't report to the DTIM that data is cacheable
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2017-08-08 11:55:04 -07:00 |
TLBPermissions.scala
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Refactor package hierarchy and remove legacy bus protocol implementations (#845)
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2017-07-07 10:48:16 -07:00 |