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526 Commits

Author SHA1 Message Date
Andrew Waterman 5cfe070932 Add option to make misa read-only 2017-10-03 17:34:18 -07:00
Andrew Waterman 09468a272b Add option to remove basic counters (mcycle/minstret) 2017-10-03 17:34:18 -07:00
Andrew Waterman ab0821f25b Move microarchitecture-neutral params from Rocket to Core 
This makes some of the units more reusable.
 2017-10-03 17:34:18 -07:00
Andrew Waterman 190d5c50d9 Remove deprecated custom-CSR support 2017-10-03 17:34:18 -07:00
Henry Cook aa3a18222c HellaCache: users like to peep resp.data and resp.addr 2017-10-02 19:36:30 -07:00
Andrew Waterman 9137f54f59 Merge pull request #1020 from freechipsproject/fix-trace-insn 
Provide correct trace insn on interrupts when possible
 2017-09-27 18:47:24 -07:00
Andrew Waterman 9eaf50762e Don't report exceptions as valid instructions in the printed log 2017-09-27 16:29:42 -07:00
Wesley W. Terpstra 0a287df0f7 Merge remote-tracking branch 'origin/master' into auto-diplomacy-bundles 2017-09-27 16:28:10 -07:00
Andrew Waterman 31c5246446 Provide correct trace insn on interrupts when possible 2017-09-27 16:27:53 -07:00
Henry Cook 05112b49a3 Merge branch 'master' into tl-error 2017-09-27 14:50:17 -07:00
Andrew Waterman 78f3877e02 Trace tval field should be zero when not taking exceptions 2017-09-27 12:51:10 -07:00
Andrew Waterman 583adeee88 Separate interrupt bit from cause field in trace bundle 2017-09-27 12:41:30 -07:00
Wesley W. Terpstra 5323cf88dd util: add Option.unzip 2017-09-25 12:06:31 -07:00
Wesley W. Terpstra 60614055e3 diplomacy: eliminate some wasted IdentityNodes using cross-module refs 2017-09-25 12:06:27 -07:00
Wesley W. Terpstra b9a2e4c243 diplomacy: API beautification 2017-09-22 15:01:42 -07:00
Wesley W. Terpstra 9217baf9d4 diplomacy: change API to auto-create node bundles => cross-module refs 2017-09-22 15:01:39 -07:00
Wesley W. Terpstra dfc815f4d3 rocket: invoke LazyModule at point of use/binding 2017-09-22 14:38:47 -07:00
Henry Cook 81e136aa37 rocket: give l2 tlb a nice name 2017-09-21 18:13:39 -07:00
Henry Cook 30c8c8c517 Revert "try to give seqmems clearer names" 
This reverts commit 8db5bbbae0.

This attempt at clarification instead results in confusing generated verilog like:
`dcache_data_arrays_0 icache_data_arrays_0 (...);`
because of deduplication of identically dimensioned SRAMs...
 2017-09-21 18:02:32 -07:00
Henry Cook a887baa615 rocket: base trait for reporting ecc errors 2017-09-21 14:58:47 -07:00
Andrew Waterman 88c782cc70 Report D$ uncorrectable errors on C channel 2017-09-20 17:15:11 -07:00
Andrew Waterman 6bc20942b5 Don't cache TL error responses; report access exceptions 2017-09-20 17:01:08 -07:00
Andrew Waterman 9b828a2640 Only look at error signal on last beat 2017-09-20 15:15:21 -07:00
Andrew Waterman 026fa14bf8 Rename trace.addr -> iaddr 2017-09-20 14:32:41 -07:00
Andrew Waterman 5b2f458214 Merge branch 'master' into ma-fetch 2017-09-20 12:18:03 -07:00
Andrew Waterman f1a506476b Merge pull request #994 from freechipsproject/beu 
Add L1 bus-error unit
 2017-09-20 12:17:08 -07:00
Andrew Waterman f5bd639863 Don't write badaddr on misaligned fetch exceptions 
It's optional, and we were doing it wrong before, so just don't do it.
 2017-09-20 10:52:41 -07:00
Andrew Waterman db57e943f3 Report TL errors into D$ 2017-09-20 00:05:07 -07:00
Andrew Waterman aaad73f019 Add an intra-tile xbar 2017-09-20 00:05:07 -07:00
Andrew Waterman afad25fceb Integrate L1 BusErrorUnit 2017-09-20 00:05:07 -07:00
Andrew Waterman 79dab487fc Implement bus error unit 2017-09-20 00:05:07 -07:00
Andrew Waterman ed18acaae0 Report D$ errors 2017-09-20 00:05:07 -07:00
Andrew Waterman 034ea722f4 Report I$ errors 2017-09-20 00:05:07 -07:00
Andrew Waterman 4d6d6ff641 Add instruction-trace port 2017-09-19 22:59:57 -07:00
Henry Cook 57e8fe0a6b Merge pull request #1000 from freechipsproject/name-seqmems 
try to give seqmems clearer names for use with external tools
 2017-09-19 17:59:00 -07:00
Henry Cook 8db5bbbae0 try to give seqmems clearer names 2017-09-19 13:41:11 -07:00
Andrew Waterman d93d7b9fa4 Only merge stores that aren't yet pending 
This fixes a deadlock (and possibly memory corruption, though that is
unconfirmed).  The following sequence manifests it, assuming t0
is 32-byte aligned:

    sw t0, 0(t0)
    sw t0, 16(t0)
    lw t1, 4(t0)
    lw t2, 4(t0)
 2017-09-17 15:01:07 -07:00
Henry Cook b86f4b9bb7 config: use Field defaults over Config defaults 
Also rename some keys that had the same class name as their value's class name.
 2017-09-13 11:25:42 -07:00
Henry Cook 063ca0ed4a Merge pull request #983 from freechipsproject/kill-paddrbits 
Remove global fields PAddrBits and ResetVectorBits
 2017-09-11 12:51:10 -07:00
Andrew Waterman 1f606d924f Don't perform in-place correction if there was a recent store (#988) 
Since the correction updates the entire word, the WAW hazard detection
logic is not sufficient to prevent overwriting a recent store.  So,
re-read the word after all pending stores have drained.
 2017-09-08 16:26:54 -07:00
Henry Cook 9c0bfbd500 tile: remove global Field ResetVectorBits 
Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
 2017-09-08 14:50:59 -07:00
Henry Cook 3133c321b7 scratchpad: remove dependency on HasCoreParameters 2017-09-08 13:55:40 -07:00
Henry Cook e46aeb7342 tile: remove PAddrBits in favor of SharedMemoryTLEdge 2017-09-08 13:53:36 -07:00
Wesley W. Terpstra e7de7f3e82 Merge pull request #985 from freechipsproject/flop-interrupts 
Add Parameters to diplomatic edges
 2017-09-08 13:16:11 -07:00
Andrew Waterman 53dfc5e9be Remove overzealous assertion (#987) 
This assertion made sure the D$ controller was able to write the tag RAM
when a cache line was refilled.  However, it is benign if it fails to do
so: the metadata is invalid at this point, so the miss will simply happen
a second time.

This happens when resolving a tag ECC error during hit-under-miss.
 2017-09-07 18:17:56 -07:00
Wesley W. Terpstra 1365c5f90c diplomacy: implement DisableMonitors scope 2017-09-07 16:03:35 -07:00
Andrew Waterman 8087a205cc Remove redundant check in interrupt priority encoding 
chooseInterrupts already sorts M interrupts above S interrupts.
 2017-08-17 22:23:42 -07:00
Andrew Waterman cbe7c51b50 Respect ISA requirements on interrupt priority order 
a62e76cb16
 2017-08-17 21:27:08 -07:00
Andrew Waterman e945f6e265 Merge pull request #955 from freechipsproject/fix-acquire-before-release 
Fix acquire before release
 2017-08-13 18:29:58 -07:00
Megan Wachs 88332bd885 max-core-cycles: Add a +max-core-cycles PlusArg 2017-08-13 15:47:14 -07:00
Andrew Waterman 3cbc5262ec Don't permit new acquires until the release queue is drained 
If the queue is not empty before a dirty miss, C could block D.
I haven't seen this in the wild, but it could happen because of
dirty probe responses backed up in the queue.
 2017-08-13 13:18:45 -07:00
Andrew Waterman 0190724492 Actually use the C-channel acquire-before-release queue 
oops...
 2017-08-13 13:03:35 -07:00
Andrew Waterman 7387f2a93a Don't block D-channel when handling a probe 
This is an acquire-before-release regression.
 2017-08-12 16:13:24 -07:00
Andrew Waterman 604abd5b07 Only report ECC errors when the RAM was actually read 2017-08-12 15:28:03 -07:00
Andrew Waterman 18fb052fc9 DRY 2017-08-12 15:27:30 -07:00
Andrew Waterman 176110b6d3 Don't trigger ECC writebacks when a release is in flight 2017-08-12 15:23:57 -07:00
Andrew Waterman 0a591c5b5b Roll back use of UIntToOH1 (#946) 
These appear to be equivalent, but the old one seems to fail in Vivado and
this one seems to pass.  This is not yet conclusive.
 2017-08-09 18:39:47 -07:00
Andrew Waterman 721770244e Fix IBuf bug 
Don't examine a packet's xcpt signal if it might be invalid.  In this case,
the correct fix is to not examine xcpt at all; the deleted code was vestigial.
(Note, the other use of xcpt(j+1) in this code is indeed safe.)
 2017-08-09 09:47:51 -07:00
Andrew Waterman 809c7e8551 Don't merge stores that manifest WAW hazards 
The following sequence would drop the first store when eccBytes=4:

    sb x0, 0(t0)
    nop
    sb x0, 4(t0)
    nop
    sb x0, 1(t0)

Because the first and second store are to different ECC granules, the
hazard check correctly allowed the second one to proceed, but the third
was merged with the second, even though it conflicted with the first.
So, don't allow the third to be merged with the second, since the second
stored to a different ECC granule.
 2017-08-08 15:19:05 -07:00
Andrew Waterman 82e13443b2 Merge pull request #937 from freechipsproject/critical-paths 
Perform tag error detectoin/correction in same cycle as RAM
 2017-08-08 15:03:28 -07:00
Andrew Waterman 7935c61c19 Don't report to the DTIM that data is cacheable 
Otherwise, it will attempt to perform AMOs where they're unsupported!
 2017-08-08 11:55:04 -07:00
Andrew Waterman 74d309c18e Make I vs. D a static property of TLB, not an input pin 
The microarchitecture doesn't really support unified TLBs, so don't fake it.
 2017-08-08 11:54:47 -07:00
Andrew Waterman e92981b0bd DRY 2017-08-08 11:46:38 -07:00
Andrew Waterman 62ccba304c Perform tag error detectoin/correction in same cycle as RAM 
The tag RAMs tend to be fast, so take up some of the slack.
This makes s2_nack faster.
 2017-08-08 10:21:30 -07:00
Palmer Dabbelt 6d1d285464 Merge pull request #933 from freechipsproject/cinst 
Print out the compressed instruction when executing one
 2017-08-07 21:40:10 -07:00
Andrew Waterman 402907990c Revert "Remove one gate from D$ ECC check" 
This reverts commit 7d94074b05, which
works fine with optimistic behavioral RAMs but not real ones.
 2017-08-07 17:33:20 -07:00
Palmer Dabbelt fc0d5fcf98 Print out the compressed instruction when executing one 2017-08-07 17:21:53 -07:00
Andrew Waterman 658e36f98b Reduce fanout on frontend io.cpu.req.valid signal 2017-08-06 17:38:51 -07:00
Andrew Waterman 7d94074b05 Remove one gate from D$ ECC check 
The D$ corrects via writeback, so which word the error was in doesn't
matter, as the entire line is corrected.
 2017-08-06 17:36:53 -07:00
Andrew Waterman 83875e3a0c Only flush D$ on FENCE.I if it won't always be probed on I$ miss 2017-08-05 14:22:40 -07:00
Andrew Waterman 991e16de92 Remove probe address mux from TLB response path 2017-08-05 12:57:38 -07:00
Andrew Waterman b9b4142bb4 Get s2_nack off the critical path 
We were using it to compute the next PC on flush vs. replay (which require
PC+4 and PC, respectively).  This fix gets rid of the adder altogether by
reusing the M-stage PC in the flush case, which by construction holds PC+4.
 2017-08-05 00:30:36 -07:00
Andrew Waterman 6112adfbb0 Get L2 TLB tag/parity check off the D$ arbitration path 2017-08-04 17:01:51 -07:00
Andrew Waterman 8d97684555 Fix L2 TLB perfctr 
It was counting conflict misses but not cold misses.
 2017-08-04 17:01:31 -07:00
Andrew Waterman df7f09b9ce Get I$ ECC check further off critical path 2017-08-04 16:59:21 -07:00
Andrew Waterman 4bfbe75d74 Avoid pipeline replays when fetch queue is full 2017-08-04 16:59:21 -07:00
Andrew Waterman a45997d03f Separate I$ parity error from miss signal 
Handle parity errors with a pipeline flush rather than a faster
frontend replay, reducing a critical path.
 2017-08-04 16:59:21 -07:00
Andrew Waterman 06a831310b Shave a gate delay off I$ backpressure path 
The deleted code was a holdover from Hwacha's vector fences.
 2017-08-04 13:12:43 -07:00
Andrew Waterman ecc2ee366c Shave a few gate delays off IBuf control logic 
It takes a while for the pipeline to compute the stall signal, so avoid
using it until the last logic levels in the clock cycle.
 2017-08-04 13:12:43 -07:00
Andrew Waterman 7937db0c84 Merge pull request #919 from freechipsproject/imiss-perf-counter 
Fix I$ miss perfctr
 2017-08-04 01:04:23 -07:00
Andrew Waterman ba4eecc0f0 Use UIntToOH1 (#921) 
Closes #920
 2017-08-03 14:55:39 -07:00
Andrew Waterman f483bab4aa Fix I$ miss perfctr 
The old version was counting prefetches, too.
 2017-08-03 00:52:12 -07:00
Andrew Waterman 1be1433f04 Merge pull request #918 from freechipsproject/icache-prefetch 
Icache prefetch
 2017-08-02 21:22:20 -07:00
Andrew Waterman 2537d0d54e Optionally prefetch next I$ line into L2$ on miss 2017-08-02 17:10:56 -07:00
Andrew Waterman 744cdb2f72 Make TLB report when it's safe to prefetch within a page 2017-08-02 17:09:38 -07:00
Andrew Waterman 7d2dd3769f Optimize a hazard check critical path 2017-08-02 14:27:25 -07:00
Andrew Waterman 2eb239d03f Add option to retime D$ way mux into subsequent pipeline stage 2017-08-01 23:59:20 -07:00
Andrew Waterman 9464c6db40 Mitigate(?) frontend critical path 2017-08-01 18:51:17 -07:00
Andrew Waterman 735701382f Mitigate some I$ response valid critical paths 2017-08-01 18:51:17 -07:00
Andrew Waterman 2ecea2ef60 Don't use a pipe queue on D$ TL A-channel 
This cuts an I$->D$ path.
 2017-08-01 15:17:07 -07:00
Andrew Waterman 5681693ccc Fix a D$ ready-valid signaling regression 
I broke this in 66d06460fa.
 2017-07-31 18:05:14 -07:00
Yunsup Lee 7adfd5c431 Merge pull request #906 from freechipsproject/critical-paths 
Mitigate I$->D$->I$ critical path
 2017-07-31 16:14:11 -07:00
Henry Cook 11332c1226 dcache: break potential combinatorial loop by making pstore_drain_on_miss more conservative 2017-07-31 14:03:30 -07:00
Andrew Waterman d811692c3b Mitigate I$->D$->I$ critical path 
This seemingly irrelevant change shaves several gate delays off the I$
tl.a.valid path.
 2017-07-31 01:43:04 -07:00
Andrew Waterman ac4339a8e7 Pass D$ backpressure to D-channel, rather than asserting 2017-07-29 11:48:36 -07:00
Andrew Waterman edcd2c696c Avoid needless stall on E-channel back pressure 2017-07-29 11:47:58 -07:00
Andrew Waterman fdb8935712 Improve fidelity of two perf counters 2017-07-28 13:14:04 -07:00
Andrew Waterman 4c82f6b77e Don't refill BTB on not-taken branches 2017-07-28 13:13:52 -07:00
Andrew Waterman 2e8b02e780 Merge D$ store hits when ECC is enabled 
This avoids pipeline flushes due to subword WAW hazards, as with
consecutive byte stores.
 2017-07-28 12:56:36 -07:00
Andrew Waterman 838864870e Bypass TLB refill signal to halve L2 TLB hit time 
The 4-cycle hit time is 1 cycle too long to avoid a second
pipeline replay, so it was effectively 9 cycles instead of 4.
 2017-07-28 12:56:36 -07:00
Andrew Waterman ae1f7a95f6 Don't nack misses when there's a pending store 
That effectively increased the miss latency by 5 cycles when there was
a store hit followed by a load miss.  Since pending stores are drained
when releaseInFlight, the check I removed was redundant.
 2017-07-28 12:56:36 -07:00
Wesley W. Terpstra 9804bdc34e tilelink: remove obsolete addr_lo signal (#895) 
When we first implemented TL, we thought this was helpful, because
it made WidthWidgets stateless in all cases. However, it put too
much burden on all other masters and slaves, none of which benefitted
from this signal. Furthermore, even with addr_lo, WidthWidgets were
information lossy because when they widen, they have no information
about what to fill in the new high bits of addr_lo.
 2017-07-26 16:01:21 -07:00
Andrew Waterman 5a5b78b15e Improve L2 TLB coding style 2017-07-26 02:22:43 -07:00
Andrew Waterman 5a9c673f41 Fix L2 TLB response bug 
Sometimes, it would inform the L1 TLB that the translation was for
a superpage, even though that's never the case.
 2017-07-26 02:20:41 -07:00
Andrew Waterman acca0fccf5 Fix BTB not being refilled on some indirect jumps 
We are overloading the BTB-hit signal to mean that any part of the frontend
changed the control-flow, not just the BTB.  That's the right thing to do for
most of the control logic, but it means the BTB sometimes won't get refilled
when we'd like it to.  This commit makes the frontend use an invalid BTB entry
number when it, rather than the BTB, changes the control flow.  Since the
entry number is invalid, the BTB will treat it as a miss and refill itself.

This is kind of a hack, but a more palatable fix requires reworking the RVC
IBuf, which I don't have time for right now.
 2017-07-26 02:13:43 -07:00
Andrew Waterman 15878d4691 Perform some control-flow transfers within the Frontend 2017-07-25 15:19:16 -07:00
Andrew Waterman 62c4080585 Add RVC instruction patterns 2017-07-25 15:19:16 -07:00
Andrew Waterman 66d06460fa Add option for acquire-before-release 2017-07-25 15:19:16 -07:00
Andrew Waterman 86ccd935fc Add method to print perf events 2017-07-25 15:19:16 -07:00
Andrew Waterman 5df8f0d1ea Add L2 TLB miss counter 2017-07-25 15:19:16 -07:00
Henry Cook 01ca3efc2b Combine Coreplex and System Module Hierarchies (#875) 
* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC
 2017-07-23 08:31:04 -07:00
Wesley W. Terpstra 4eface8a9e rocket: do not require FIFO order for memory-like regions 2017-07-12 17:39:00 -07:00
Henry Cook 4c595d175c Refactor package hierarchy and remove legacy bus protocol implementations (#845) 
* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package
 2017-07-07 10:48:16 -07:00
Andrew Waterman a0cbc376b4 Merge pull request #849 from freechipsproject/l2-tlb 
L1 memory system improvements
 2017-07-06 13:03:06 -07:00
Andrew Waterman e1cc0a0a0e Mask debug interrupts similarly to other interrupts (#847) 
This makes single-step exceptions higher-priority than debug interrupts.
 2017-07-06 12:03:24 -07:00
Andrew Waterman b2351c5fbf Use consistent casing 2017-07-06 11:16:56 -07:00
Andrew Waterman be4eceec0d Fix stupid D$ probe bug 2017-07-06 01:20:47 -07:00
Andrew Waterman 90a7d6a343 Add L2 TLB option 2017-07-06 01:19:18 -07:00
Andrew Waterman 438abc76d2 Handle TL errors in L1 I$ 
Cache the error bit in the tag array; report precisely on access.
 2017-07-06 01:02:11 -07:00
Andrew Waterman 0ef45fac9b Add tag ECC to D$ 2017-07-03 18:16:37 -07:00
Andrew Waterman e9752f76ae Improve probe state machine 
- Reduce reliance on s2_prb_ack_data due to future ECC changes
- Shave a cycle off valid, but clean, probes
- Code cleanup
 2017-07-03 16:25:04 -07:00
Richard Xia 5b46350bc3 Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment. 2017-06-30 17:44:16 -07:00
Wesley W. Terpstra 5edc4546e3 rocket: add dtim and itim refs to cpus 2017-06-28 23:10:58 -07:00
Wesley W. Terpstra 7d6f8d48f2 Revert "rocket: link dtim to its cpu" 
This reverts commit e6c2d446cc.
 2017-06-28 23:10:57 -07:00
Wesley W. Terpstra fbcd6f0eb2 Revert "rocket: link itim to its cpu" 
This reverts commit 48390ed604.
 2017-06-28 23:10:57 -07:00
Henry Cook 6e5a4c687f diplomacy: a type of connect that always disables monitors (#828) 2017-06-28 21:48:10 -07:00
Megan Wachs 992b480c74 Merge pull request #825 from freechipsproject/debug_wfi 
Debug + WFI Interactions
 2017-06-28 21:28:51 -07:00
Wesley W. Terpstra ca3030cba3 dcache: fix a gender inversion bug introduced in #826 2017-06-28 15:38:53 -07:00
Wesley W. Terpstra 48390ed604 rocket: link itim to its cpu 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra e6c2d446cc rocket: link dtim to its cpu 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra 3f6d5110cd rocket: dtim is not a dcache 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra 84dc23c215 devices: add reg-names to most devices 2017-06-28 15:06:16 -07:00
Wesley W. Terpstra 852f03282f rocket: give itim and dtim a compatible field for drivers to match 2017-06-28 14:26:55 -07:00
Andrew Waterman b9a934ae28 Support eccBytes > 1 2017-06-28 02:09:18 -07:00
Andrew Waterman 8e4be40efc Propagate wb_reg_rs2 for sfence ASID 
This would have been a bug if we supported ASIDs.
 2017-06-28 02:09:18 -07:00
Andrew Waterman 2077e4190b Make log more sensible for long-latency operations 
Show only one write to the destination register, not two.
 2017-06-28 02:09:18 -07:00
Andrew Waterman 6f8fdff762 Basic L1 D$ ECC support 
Only supports ECC on data, not tags; only supports byte granularity.
 2017-06-28 02:09:18 -07:00
Andrew Waterman 6100600179 Minor D$ code cleanup 2017-06-28 02:09:18 -07:00
Andrew Waterman 3e04a99f61 Refactor frontend exception passing 
Bundle them, and leverage regularity, so that if we have to add more
exceptions in the future, we don't need to change so much code.
 2017-06-28 02:09:18 -07:00
Andrew Waterman cc2f87c214 Forbid S-mode execution from user memory 
285c81746f
 2017-06-28 02:09:18 -07:00
Andrew Waterman 8aa16a11f3 Reduce D$ access energy when refill width > access width 2017-06-28 02:09:18 -07:00
Andrew Waterman 25f585f2a9 Remove unused signal from TLB interface 2017-06-28 02:09:18 -07:00
Andrew Waterman d5f80df0ae Allow speculative I$ refill to cacheable regions 
Backpedaling on 27b143013f.  Shaving
four cycles off of I$ miss penalty is obviously worth the HW cost.
 2017-06-28 02:09:18 -07:00
Megan Wachs e1fe0f245b debug: Don't reset debugint register, as none of the interrupt registers are. 2017-06-27 14:10:13 -07:00
Megan Wachs 136e4b6c27 debug: use consistent coding style (Reg(init ... ) vs RegInit) 2017-06-27 13:42:38 -07:00
Megan Wachs 3b9550ede3 debug: correctly declare reg_debugint 2017-06-27 13:42:38 -07:00
Megan Wachs 56839b2c62 debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec) 2017-06-27 13:42:38 -07:00
Megan Wachs 665c2a349c Correct Debug + WFI Interactions 
1) Debug interrupt should end WFI
2) WFI should end immedately during single-step
3) WFI should act like NOP during Debug Mode
 2017-06-27 13:42:38 -07:00
Zihao Yu c9cfe46604 rocket,Rocket: fix type mismatch (#819) 2017-06-27 11:22:08 -07:00
Colin Schmidt aced18b3bb Move RoCC interface to Diplomacy and TL2 (#807) 
* Move RoCC interface to Diplomacy and TL2

* guard rocc arbiter to prevent zero-width wires
 2017-06-22 12:07:09 -07:00