ae1f7a95f6
Don't nack misses when there's a pending store
...
That effectively increased the miss latency by 5 cycles when there was
a store hit followed by a load miss. Since pending stores are drained
when releaseInFlight, the check I removed was redundant.
2017-07-28 12:56:36 -07:00
9804bdc34e
tilelink: remove obsolete addr_lo signal ( #895 )
...
When we first implemented TL, we thought this was helpful, because
it made WidthWidgets stateless in all cases. However, it put too
much burden on all other masters and slaves, none of which benefitted
from this signal. Furthermore, even with addr_lo, WidthWidgets were
information lossy because when they widen, they have no information
about what to fill in the new high bits of addr_lo.
2017-07-26 16:01:21 -07:00
5a5b78b15e
Improve L2 TLB coding style
2017-07-26 02:22:43 -07:00
5a9c673f41
Fix L2 TLB response bug
...
Sometimes, it would inform the L1 TLB that the translation was for
a superpage, even though that's never the case.
2017-07-26 02:20:41 -07:00
acca0fccf5
Fix BTB not being refilled on some indirect jumps
...
We are overloading the BTB-hit signal to mean that any part of the frontend
changed the control-flow, not just the BTB. That's the right thing to do for
most of the control logic, but it means the BTB sometimes won't get refilled
when we'd like it to. This commit makes the frontend use an invalid BTB entry
number when it, rather than the BTB, changes the control flow. Since the
entry number is invalid, the BTB will treat it as a miss and refill itself.
This is kind of a hack, but a more palatable fix requires reworking the RVC
IBuf, which I don't have time for right now.
2017-07-26 02:13:43 -07:00
15878d4691
Perform some control-flow transfers within the Frontend
2017-07-25 15:19:16 -07:00
62c4080585
Add RVC instruction patterns
2017-07-25 15:19:16 -07:00
66d06460fa
Add option for acquire-before-release
2017-07-25 15:19:16 -07:00
86ccd935fc
Add method to print perf events
2017-07-25 15:19:16 -07:00
5df8f0d1ea
Add L2 TLB miss counter
2017-07-25 15:19:16 -07:00
01ca3efc2b
Combine Coreplex and System Module Hierarchies ( #875 )
...
* coreplex collapse: peripherals now in coreplex
* coreplex: better factoring of TLBusWrapper attachement points
* diplomacy: allow monitorless :*= and :=*
* rocket: don't connect monitors to tile tim slave ports
* rename chip package to system
* coreplex: only sbus has a splitter
* TLFragmenter: Continuing my spot battles on requires without explanatory strings
* pbus: toFixedWidthSingleBeatSlave
* tilelink: more verbose requires
* use the new system package for regression
* sbus: add more explicit FIFO attachment points
* delete leftover top-level utils
* cleanup ResetVector and RTC
2017-07-23 08:31:04 -07:00
4eface8a9e
rocket: do not require FIFO order for memory-like regions
2017-07-12 17:39:00 -07:00
4c595d175c
Refactor package hierarchy and remove legacy bus protocol implementations ( #845 )
...
* Refactors package hierarchy.
Additionally:
- Removes legacy ground tests and configs
- Removes legacy bus protocol implementations
- Removes NTiles
- Adds devices package
- Adds more functions to util package
2017-07-07 10:48:16 -07:00
a0cbc376b4
Merge pull request #849 from freechipsproject/l2-tlb
...
L1 memory system improvements
2017-07-06 13:03:06 -07:00
e1cc0a0a0e
Mask debug interrupts similarly to other interrupts ( #847 )
...
This makes single-step exceptions higher-priority than debug interrupts.
2017-07-06 12:03:24 -07:00
b2351c5fbf
Use consistent casing
2017-07-06 11:16:56 -07:00
be4eceec0d
Fix stupid D$ probe bug
2017-07-06 01:20:47 -07:00
90a7d6a343
Add L2 TLB option
2017-07-06 01:19:18 -07:00
438abc76d2
Handle TL errors in L1 I$
...
Cache the error bit in the tag array; report precisely on access.
2017-07-06 01:02:11 -07:00
0ef45fac9b
Add tag ECC to D$
2017-07-03 18:16:37 -07:00
e9752f76ae
Improve probe state machine
...
- Reduce reliance on s2_prb_ack_data due to future ECC changes
- Shave a cycle off valid, but clean, probes
- Code cleanup
2017-07-03 16:25:04 -07:00
5b46350bc3
Make sure that DCache s2_xcpt data scratchpad case is assigned to after initial assignment.
2017-06-30 17:44:16 -07:00
5edc4546e3
rocket: add dtim and itim refs to cpus
2017-06-28 23:10:58 -07:00
7d6f8d48f2
Revert "rocket: link dtim to its cpu"
...
This reverts commit e6c2d446cc
2017-06-28 23:10:57 -07:00
fbcd6f0eb2
Revert "rocket: link itim to its cpu"
...
This reverts commit 48390ed604
2017-06-28 23:10:57 -07:00
6e5a4c687f
diplomacy: a type of connect that always disables monitors ( #828 )
2017-06-28 21:48:10 -07:00
992b480c74
Merge pull request #825 from freechipsproject/debug_wfi
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Debug + WFI Interactions
2017-06-28 21:28:51 -07:00
ca3030cba3
dcache: fix a gender inversion bug introduced in #826
2017-06-28 15:38:53 -07:00
48390ed604
rocket: link itim to its cpu
2017-06-28 15:06:19 -07:00
e6c2d446cc
rocket: link dtim to its cpu
2017-06-28 15:06:19 -07:00
3f6d5110cd
rocket: dtim is not a dcache
2017-06-28 15:06:19 -07:00
84dc23c215
devices: add reg-names to most devices
2017-06-28 15:06:16 -07:00
852f03282f
rocket: give itim and dtim a compatible field for drivers to match
2017-06-28 14:26:55 -07:00
b9a934ae28
Support eccBytes > 1
2017-06-28 02:09:18 -07:00
8e4be40efc
Propagate wb_reg_rs2 for sfence ASID
...
This would have been a bug if we supported ASIDs.
2017-06-28 02:09:18 -07:00
2077e4190b
Make log more sensible for long-latency operations
...
Show only one write to the destination register, not two.
2017-06-28 02:09:18 -07:00
6f8fdff762
Basic L1 D$ ECC support
...
Only supports ECC on data, not tags; only supports byte granularity.
2017-06-28 02:09:18 -07:00
6100600179
Minor D$ code cleanup
2017-06-28 02:09:18 -07:00
3e04a99f61
Refactor frontend exception passing
...
Bundle them, and leverage regularity, so that if we have to add more
exceptions in the future, we don't need to change so much code.
2017-06-28 02:09:18 -07:00
cc2f87c214
Forbid S-mode execution from user memory
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285c81746f
2017-06-28 02:09:18 -07:00
8aa16a11f3
Reduce D$ access energy when refill width > access width
2017-06-28 02:09:18 -07:00
25f585f2a9
Remove unused signal from TLB interface
2017-06-28 02:09:18 -07:00
d5f80df0ae
Allow speculative I$ refill to cacheable regions
...
Backpedaling on 27b143013f
2017-06-28 02:09:18 -07:00
e1fe0f245b
debug: Don't reset debugint register, as none of the interrupt registers are.
2017-06-27 14:10:13 -07:00
136e4b6c27
debug: use consistent coding style (Reg(init ... ) vs RegInit)
2017-06-27 13:42:38 -07:00
3b9550ede3
debug: correctly declare reg_debugint
2017-06-27 13:42:38 -07:00
56839b2c62
debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec)
2017-06-27 13:42:38 -07:00
665c2a349c
Correct Debug + WFI Interactions
...
1) Debug interrupt should end WFI
2) WFI should end immedately during single-step
3) WFI should act like NOP during Debug Mode
2017-06-27 13:42:38 -07:00
c9cfe46604
rocket,Rocket: fix type mismatch ( #819 )
2017-06-27 11:22:08 -07:00
aced18b3bb
Move RoCC interface to Diplomacy and TL2 ( #807 )
...
* Move RoCC interface to Diplomacy and TL2
* guard rocc arbiter to prevent zero-width wires
2017-06-22 12:07:09 -07:00
5552f23294
tims: explictly name them for generated address map
2017-06-20 17:18:29 -07:00
6b79842e66
dcache: just left shift by untagbits to get tag
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Always safe because of the requirement on coreplex/RocketTiles.scala:126
2017-06-20 16:35:28 -07:00
f396b4142d
Merge pull request #806 from freechipsproject/mulh
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Improve integer mul/div
2017-06-20 13:01:16 -07:00
675f183dd2
refactor ICache to be reusable by other frontends ( #808 )
...
* refactor ICache to be reusable by other frontends
specifically one that would like to change the fetch width and number of
bytes in an instruction
2017-06-20 08:21:01 -07:00
a6d9884cc0
Improve integer mul/div
...
- Signed integer multiplication latency is now deterministic (before,
it would take an extra cycle if the multiplier was negative).
- High-part multiplication is now one cycle faster.
- RV64 MULW now takes half as many cycles as MUL.
- Positive remainders are now one cycle faster.
2017-06-19 12:09:21 -07:00
61c39da475
Check for rvc before declaring illegal instruction after an ebreak.
2017-06-16 10:49:36 -07:00
8552c77972
Fix I$ reset regression FU-357
...
Can't rely on s2 TLB response, so mask using s2_valid.
2017-06-09 00:48:24 -07:00
16ecbdd5b2
Reduce fanout on critical I$ miss signal
2017-06-02 20:45:50 -07:00
27b143013f
Improve ITLB QoR
...
- No need to check cacheability
- Remove a gate delay from PMP path
2017-06-02 20:45:50 -07:00
80c63c0da6
rocket: include hartid in cache master names
2017-06-02 15:52:23 -07:00
d25ad10592
diplomacy: require masters to have a name
2017-06-02 15:52:20 -07:00
0fe625c52f
diplomacy: improve PMA circuit QoR
2017-06-01 15:30:20 -07:00
e3e77d68e6
PTW now does not require atomic memory operations, so take out the requirement ( #767 )
...
Bug fix in CSR which manifest itself when compiling a config with no extension
2017-05-26 13:11:15 -07:00
dbc5e7c494
Add TLB miss performance counters ( #762 )
2017-05-23 12:52:25 -07:00
b2b4c1abcd
Separate tag ECC and data ECC options ( #761 )
2017-05-23 12:51:48 -07:00
a19fc2549e
tile: add tileBus xbar
2017-05-16 16:12:01 -07:00
18725a05b0
DTS tweaks ( #740 )
...
* rocket: do not report 's' in isa string
* rocket: report the micro-architecture of the core
2017-05-12 05:32:57 -07:00
7eefc12705
Support vectored stvec interrupts, too
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137812654e
2017-05-07 15:40:08 -07:00
c6135a02df
Revert "rocket: hard-wire UXL/SXL fields to 0"
...
This reverts commit ea0714bfcb326bec83de
2017-05-07 15:23:21 -07:00
dd1546fd69
Check PPN LSBs for superpage PTEs
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5a32fe8782
2017-05-05 15:30:09 -07:00
1b3b228790
ITIM supports PutPartial
2017-05-04 00:57:52 -07:00
398600d4da
Interlock to prevent ITIM hazard when tl.a.valid & tl.d.valid & !tl.d.ready
2017-05-04 00:57:29 -07:00
fa6ecdf813
Fix RVC/uncacheable instruction memory performance bug
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9c1d126965
2017-05-03 17:52:06 -07:00
f8c92d2669
Merge branch 'master' into pipeline-mmio
2017-05-03 08:37:12 -07:00
4efcb5a139
Increase frontend decoupling ( #722 )
...
Reduce pathological RVC stalls
2017-05-03 07:54:46 -07:00
4dd3345db2
Merge branch 'master' into pipeline-mmio
2017-05-02 16:23:26 -07:00
3a1a37d41b
Support PutPartial in ScratchpadSlavePort
2017-05-02 03:07:02 -07:00
f8151ce786
Remove subword load muxing in ScratchpadSlavePort
2017-05-02 00:14:46 -07:00
f49172b5bc
ScratchpadSlavePort doesn't support byte/halfword atomics
2017-05-02 00:14:46 -07:00
3d06f01a2c
rocket: turn on early ack for ITIM
2017-05-01 22:53:41 -07:00
30f1f1e7c7
rocket: turn on early ack for DTIM
2017-05-01 22:53:41 -07:00
d6e69066a5
Fix ITIM loads ( #716 )
...
An incorrectly-set ready signal caused bad data to be read from the RAM.
2017-05-01 17:41:25 -07:00
dd85d7e0a0
I$: Don't raise io.resp.valid if io.s1_kill was high previous cycle
...
@solomatnikov found the bug. It doesn't manifest in Rocket because the
Frontend masks io.resp.valid with s2_valid.
2017-04-28 16:44:58 -07:00
d67738204f
Interrupts: Less Pessimistic Synchronization ( #714 )
...
* interrupts: Less pessimistic synchronization for the different interrupt types. There are some issues with the interrupt number assignments.
* interrupts: Allow an option to NOT synchronize all the external interrupts coming into PLIC
* interrupts: ExampleRocketChipTop uses PeripheryAsyncExtInterrupts. Realized 'abstract' doesn't do what I thought in Scala.
* interrupts: use consistent async/periph/core ordering
* interrupts: Properly condition on 0 External interrupts
* interrupts: CLINT is also synchronous to periph clock
2017-04-28 14:49:24 -07:00
7416f2a17e
Unbreak groundtest
2017-04-28 02:10:33 -07:00
8fd5ecdff8
Set io.cpu.resp.bits.addr for MMIO loads without affecting QoR
2017-04-27 19:50:38 -07:00
3d0ed80ef6
new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels
2017-04-27 18:17:31 -07:00
99de42d34c
Swap order of ITIM WidthWidget and Fragmenter
...
e99fa057ac
2017-04-27 15:30:02 -07:00
8c10caeef9
Express PMP mask generation with incrementer, not adder
...
DC apparently doesn't always pick up the ((x + 1) ^ x) idiom.
Use (x + ~(x + 1)) instead.
2017-04-27 15:16:29 -07:00
e99fa057ac
cleanup scratchpad nodes
2017-04-27 14:02:05 -07:00
b2b4725522
Fix zero-width wire issues when ITIM is disabled
2017-04-26 22:43:00 -07:00
e23ee274f6
Size hartid field with NTiles, not XLen
2017-04-26 20:11:43 -07:00
dc753bfa95
Fix I$ elaboration when ITIM is disabled
2017-04-26 19:35:35 -07:00
80d826b94a
Make DTIM deduplicatable
2017-04-26 19:35:35 -07:00
418879a47f
Add Instruction Tightly Integrated Memory
2017-04-26 19:35:35 -07:00
f3ab23d068
dcache: fix stupidly wrong crossing comparison ( #703 )
2017-04-25 09:18:41 -07:00
4807ce7ced
dcache: put a flow Q to absorb back-pressure without restarting pipeline ( #701 )
...
* dcache: put a flow Q to absorb back-pressure without restarting pipeline
When used with a RationalCrossing, pipelined MMIO does not come out cleanly.
The first beat works, but if the second beat gets stalled, the pipeline is
restarted. This is a quick hacky test to absorb the beats. Perhaps a better
fix can be made to achieve the same effect.
* dcache: provision as few stages as possible
2017-04-24 23:28:04 -07:00
9c1d126965
Allow speculative fetch to uncacheable memory if it hits in I$ ( #700 )
...
@aswaterman it's in
2017-04-24 19:12:37 -07:00
65928dc6a0
Don't push RAS for "auipc ra, X; jalr ra, ra, Y"
2017-04-24 02:01:15 -07:00
36a7971975
Bypass scoreboard to reduce MMIO latency
2017-04-24 02:01:15 -07:00
f2d4cb8152
Update RAS speculatively from fetch stage
2017-04-24 02:01:15 -07:00
c36c171202
Use correct interrupt priority order
2017-04-24 02:01:15 -07:00
bf861293d9
Add ShiftQueue; use it
2017-04-24 02:01:15 -07:00
d24d8ff84b
Don't stall the frontend, making it easier to add more features later
2017-04-24 02:01:15 -07:00
061a0adceb
Fetch smaller parcels from the I$
2017-04-24 02:01:15 -07:00
c72b15f2a0
Down with any require() statement that makes me RTFC
2017-04-21 15:44:42 -07:00
67404a665b
When not using a cache, LR/SC isn't legal even on cacheable memory
2017-04-20 08:47:03 -07:00
d82a0dc231
Mitigate D$ exception critical path, yet again
2017-04-18 00:47:58 -07:00
c99ce7ce5d
Only report D$ exceptions on not-nacked accesses
2017-04-18 00:47:58 -07:00
a956b78dd2
In TLBPermissions, merge across some region types
...
We only care whether they have side effects or not.
2017-04-18 00:47:58 -07:00
6de6f38894
Pipeline D$ exception response into s2
2017-04-18 00:47:58 -07:00
cc9ec1d51a
Send D$ grant acks early; accept release acks early
...
We now need to block the B-channel for a few cycles after a grant to
allow the processor to get at least one request through, preventing
livelock.
2017-04-18 00:47:58 -07:00
728569c717
Reduce access-exception generation critical path
2017-04-18 00:47:58 -07:00
c366007a0d
Tighten PMAs for LR/SC and misaligned accesses
...
- LR/SC on cacheable memory only (not even scratchpad)
- No misaligned accesses on regions with get/put-effects
2017-04-18 00:47:58 -07:00
74a7838de0
In TLBPermissions, don't merge regions of different types
2017-04-18 00:47:58 -07:00
7871ec82c4
Guarantee probe forward progress during LR storm
2017-04-18 00:47:58 -07:00
debcbca7de
Make PMP tolerant to PA size << VA size
2017-04-17 10:28:33 -07:00
a454edaaf7
Treat exceptions as steps for the purposes of single-stepping
2017-04-17 10:28:33 -07:00
2f22fca615
rocket: reverse input edge for better output
2017-04-14 18:09:14 -07:00
fdfcffb0b2
Catch bad physical address MSBs when VA size > PA size
2017-04-14 01:03:11 -07:00
6fbbccca3e
Improve Seq indexing QoR
2017-04-14 01:03:11 -07:00
d203c4c654
Check AMO operation legality in TLB
2017-04-14 01:03:11 -07:00
6359ff96e5
Several ScratchpadSlavePort bug fixes ( #676 )
...
* only replicate scratch slave d-channel resp when AMO req
* dtim: port can't support put partial mask with holes
* dtim: use \!isRead instead of isAMO
* Fix ScratchpadSlavePort looking at wrong Acquire message
Rename acq to a in the helper method.
Delete isRead and isWrite altogether.
2017-04-13 23:25:51 -07:00
b9e042d2bf
Unconditionally write badaddr, possibly to zero
...
59d33f6b83
2017-04-12 13:35:02 -07:00
470c6711a7
Do some CSE by hand, per @terpstra
2017-04-10 22:38:25 -07:00
a43bf2feae
Add vectored interrupt support
...
4dcaa944baba6d88466a
2017-04-08 00:29:45 -07:00
c861c4925e
Don't signal access exceptions on invalid PTEs
...
The PPN should not be interpreted in this case.
2017-04-05 21:46:55 -07:00
2e09253d26
Revive I$ parity option
...
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
2017-04-05 21:46:55 -07:00
43917dd59f
Get I$ s1_kill signal off the critical path
2017-04-05 21:46:55 -07:00
744fb2e4b9
Cut imem.resp.ready critical path with a flow queue
...
This is only necessary for RVC, where the decode latency is much higher.
2017-04-05 21:46:55 -07:00
3e72f9779f
Handle single-step with a pipeline stall, not a flush
...
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
2017-04-05 19:52:44 -07:00
127f121ef2
Preserve id_do_fence ( #651 )
2017-04-05 08:29:45 -07:00
19f0ae64a0
Only set id_reg_fence when AMO/FENCE is actually executed
...
This is a performance bug, not a correctness bug. But randomly stalling
because of garbage bits coming out of the I$ should be avoided.
h/t @solomatnikov
2017-04-03 21:13:52 -07:00
410e9cf736
I$ bugfix, to be reworked
2017-03-31 12:17:41 -07:00
b9550e8523
Merge branch 'master' into name-rams
2017-03-30 17:36:01 -07:00
a8a2ee711c
Give I$ RAMs consistent names
2017-03-30 15:50:54 -07:00
2720095b8e
Give D$ RAMs consistent names
2017-03-30 15:49:14 -07:00
70e7e90c02
Remove splitMetadata option from L1 caches
...
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
2017-03-30 15:48:55 -07:00
9de06f8c83
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-30 08:01:11 -07:00
fd39eadcd6
New PMP encoding
2017-03-30 00:36:23 -07:00
2f2b472098
rocket: split the interrupt controller into its own node
2017-03-30 00:36:23 -07:00
3546c8d133
If any PMPs are supported, all CSRs exist
2017-03-30 00:36:23 -07:00
8f73a58d90
Report access exception, not page fault, if page-table walk fails
2017-03-30 00:36:23 -07:00
25232070ec
Don't redundantly set resp_ae in PTW
2017-03-30 00:36:23 -07:00
d3bc99e253
get local interrupts out of the tile
2017-03-30 00:36:23 -07:00
0b9fc94421
Assertion for back-to-back uncached and cached ops ( #631 )
2017-03-29 23:07:17 -07:00
d8033b20fc
Merge remote-tracking branch 'origin/master' into debug_v013_pr
2017-03-29 14:58:04 -07:00
44fb3be7d0
Fix MMIO/cache refill concurrency bug in DCache
...
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
2017-03-28 17:16:29 -07:00
4215f480ef
Write instruction to badaddr on illegal instruction traps
2017-03-28 00:56:14 -07:00
bb64c92906
csr: Bring functionality in line with v13 spec. ebreak does not cause exception in Debug Mode, it just starts at Debug ROM again.
2017-03-27 21:21:48 -07:00
05cbdced78
Work around zero-entry vec issue in Chisel
2017-03-27 17:57:26 -07:00
d42d8aaea7
Make SEIP writable
2017-03-27 16:37:09 -07:00
c7c357e716
Add local interrupts to core (but not yet to coreplex)
2017-03-27 16:37:09 -07:00
069858a20c
rocket: separate page faults from physical memory access exceptions
2017-03-27 16:37:09 -07:00
ea0714bfcb
rocket: hard-wire UXL/SXL fields to 0
...
a2a3346e73
2017-03-27 16:37:09 -07:00
75eba294ec
DCache: Release from the correct ID as well
2017-03-27 16:30:46 -07:00
4959771c97
Revert "For D$, use source 0 through N-1 for MMIO, not 1 through N"
...
This reverts commit 0538dc77ce
2017-03-27 16:30:46 -07:00
fa7ead6357
Revert "Use Reg(Vec) instead of Seq(Reg) for DCache MMIO"
...
This reverts commit fb6498f2c3
2017-03-27 16:30:46 -07:00
08c4f7cea6
RocketTile: Create a wrapper for SyncRocketTile as well ( #616 )
...
* RocketTile: Create a wrapper for SyncRocketTile as well
There is no guarantee that debugInterrupt is synchronous
to tlClk, even though it is true in the current implementation.
It will not be true in future implementations, as decoupling
this allows the debugInterrupt to be asserted across tlClk
gating/reset scenarios.
Therefore, even for SyncRocketTile, the debug interrupt needs to be
synchronized to coreClk, and for RationalRocketTile, 1 cycle
of synchronization is not sufficient.
Even though other interrupts may be synchronized, we just
synchronize them all to simplify the code at the expense of
a few cycles latency.
It could still be nice to use a parameter vs hard coding "3".
* RocketTile: Actually use the SyncRocketTile wrapper to get properly synchronized resets.
2017-03-27 02:45:37 -07:00
5d1165c850
Express PMP mask generator using a carry chain
...
This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
2017-03-26 14:20:16 -07:00
996a31364a
rocket: remove hard-coded paddrBits ( #610 )
...
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
2017-03-24 22:30:18 -07:00
17b1ee3037
Default to 8 PMPs; support 0 PMPs
2017-03-24 16:39:52 -07:00
97006ab396
Don't modulate PMP privilege on passsthrough when !usingVM
2017-03-24 16:39:52 -07:00
3f0d2fe826
Instantiate PTW unconditionally
...
This keeps the PMP datapaths intact. The PTW itself will get optimized
away for the !usingVM case.
2017-03-24 16:39:52 -07:00
30415215b8
Don't check for exceptions on ScratchpadSlavePort accesses
2017-03-24 16:39:52 -07:00
ccd5bc9a91
Improve QoR of PMP homogeneity checker
2017-03-24 16:39:52 -07:00
e9cadf29d2
Improve DCache MMIO QoR
...
No need to store the cmd field. From the perspective of the cache, all
MMIO responses that have data can be treated the same as loads.
2017-03-24 16:39:52 -07:00
fb6498f2c3
Use Reg(Vec) instead of Seq(Reg) for DCache MMIO
2017-03-24 16:39:52 -07:00
0538dc77ce
For D$, use source 0 through N-1 for MMIO, not 1 through N
...
This makes the code a bit cleaner.
2017-03-24 16:39:52 -07:00
3951e57789
Force each TLB entry into its own clock-gate group
...
This ameliorates a PMP critical path.
I can't figure out how to do this without asUInt/asTypeOf.
2017-03-24 16:39:52 -07:00
8d7f1d777e
Fix an embarrassing typo in the PMPHeterogeneityChecker
2017-03-24 16:39:52 -07:00
10c39cb8d6
Disable mprv in D-mode
2017-03-24 16:39:52 -07:00
d3bda9574c
Put page homogeneity checker in PMP
...
Avoids redundancy between ITLB and DTLB
2017-03-24 16:39:52 -07:00
9e05200e51
Don't require that PMP ranges be aligned to access size
...
e.g., if a range permits access to 0x0-0xb, allow 8-byte accesses 0x0-0x7.
2017-03-24 16:39:52 -07:00
29e67279ba
add comments
2017-03-24 16:39:52 -07:00
4c8be13a4d
Improve homogeneity circuit QoR
2017-03-24 16:39:52 -07:00
59d6afa132
mideleg/medeleg not present without less-privileged traps
2017-03-24 16:39:52 -07:00
38808f55d5
Share PMP mask gen between I$ and D$
2017-03-24 16:39:52 -07:00
86d84959cf
More WIP on PMP
2017-03-24 16:39:52 -07:00
2888779422
Flush pipeline from WB stage, not MEM
...
Fixes sptbr write -> instruction translation hazard.
2017-03-24 16:39:52 -07:00
44ca3b60ab
Retime PTW response valid bits
...
It's not just to save the gate delay; it also reduces wire delay by
allowing the flops to be closer to their respective TLBs.
2017-03-24 16:39:52 -07:00
a03556220c
Default TLB size = 32
...
@davidbiancolin
2017-03-24 16:39:52 -07:00
1875407316
Get TLB permission checks off D$ clock gating critical path
2017-03-24 16:39:52 -07:00
a4164348b4
Expose MXR to S-mode
2017-03-24 16:39:52 -07:00
0380aed329
PUM -> SUM
2017-03-24 16:39:52 -07:00
29414f3a23
Simplify interrupt-stack discipline
...
f2ed45b179
2017-03-24 16:39:52 -07:00
723352c3e2
Mitigate some more PMP critical paths
2017-03-24 16:39:52 -07:00
7484f27ed3
Don't gate exception-cause pipeline registers separately
...
They are too narrow to justify gating separately from the other pipeline
registers (and one of the clock gates was on the PMP critical path).
2017-03-24 16:39:52 -07:00
487b8db5ef
Address some PMP critical paths
2017-03-24 16:39:52 -07:00
03fb334c4c
Take mprv calculation off critical path
2017-03-24 16:39:52 -07:00
f0796f0509
Pass correct access size information to PMP checker
2017-03-24 16:39:52 -07:00
a6874c03f7
Remove DecoupledTLB
2017-03-24 16:39:52 -07:00
78f9f6b9ef
When SFENCE.VMA has rs2 != x0, don't flush global mappings
2017-03-24 16:39:52 -07:00
1b950128e1
PTW should always use S-mode privilege
...
If an exception occurs while a page-table walk is coincidentally in
progress (e.g., an illegal instruction executes during data TLB refill),
then the processor might enter M-mode. However, the PTW's accesses
should proceed without M privilege, to avoid bypassing PMPs.
Note, the same argument doesn't apply to the nonblocking cache's replay
queues, because those accesses have already been checked against the PMPs.
The cache correctly ignores access exceptions reported on replays,
provided no exceptions were reported on the initial access.
2017-03-24 16:39:52 -07:00
aace526857
WIP on PMP
2017-03-24 16:39:52 -07:00
b1b405404d
Set PRV=M when entering debug mode
...
Debug mode mostly behaves like M-mode, so this approach avoids having
to check the debug bit in most permission checks.
2017-03-24 16:39:52 -07:00
cf168e419b
Support SFENCE.VMA rs1 argument
...
This one's a little invasive. To flush a specific entry from the TLB, you
need to reuse its CAM port. Since the TLB lookup can be on the critical
path, we wish to avoid muxing in another address.
This is simple on the data side, where the datapath already carries rs1 to
the TLB (it's the same path as the AMO address calculation). It's trickier
for the I$, where the TLB lookup address comes from the fetch stage PC.
The trick is to temporarily redirect the PC to rs1, then redirect the PC
again to the instruction after SFENCE.VMA.
2017-03-24 16:39:52 -07:00
055b8ba1f0
rocket: avoid LinkedHashMap.keys to preserve traversal order ( #603 )
2017-03-22 14:38:33 -07:00
3609254e4a
There's no structural hazard on MMIO store responses
...
So don't stall as though there were.
2017-03-21 14:17:32 -07:00
5eae7e1da4
make DCache s1_nack less conservative for pipelined MMIO requests
2017-03-21 11:16:51 -07:00
4c00066746
rocket: describe dcache as two clients (fifo+cached)
2017-03-21 11:16:51 -07:00
278f6fea24
tilelink2: define is{Request,Response} based on spec
2017-03-20 13:41:02 -07:00
0c92283a61
rocket icache: tie off b ready
2017-03-19 17:18:50 -07:00
d6f571cbbb
Implement mstatus.TSR
2017-03-13 14:50:06 -07:00
1fea0460ba
Support superpage entries in TLB
2017-03-13 14:50:06 -07:00
2d267b4940
Support corner cases in TLBPermissions
...
Don't crap out if the yes-set or no-set is empty.
2017-03-13 14:50:06 -07:00
c847559853
TLB: add a helper API to determine homogeneous page permissions
2017-03-13 14:50:06 -07:00
dbc8f4b30b
last => done
2017-03-10 15:58:38 -08:00
380c10f7bd
Zap conflicting TLB entries, preparing for superpage support
...
Superpages create the possibility that two entries in the TLB may match.
This corresponds to a software bug, but we can't return complete garbage;
we must return either the old translation or the new translation. This
isn't compatible with the Mux1H approach. So, flush the TLB and report
a miss on duplicate entries.
2017-03-10 15:58:23 -08:00
b24c43badb
Don't double-count release traffic in perfctrs
2017-03-09 16:49:02 -08:00
4f8f05d635
Add performance counter facility
2017-03-09 13:58:50 -08:00
24a2278fc4
Perform all illegal-instruction detection in ID stage
...
This is simpler, reduces what would have become a critical path in
the commit stage, and will make it easier to support the mbadinst
CSR if it is implemented.
2017-03-09 11:29:51 -08:00
7668827741
Support unrolling the integer divider
2017-03-09 11:29:51 -08:00
74d8d672bf
Improve BTB critical path at slight accuracy cost
...
Make entries fully associative on lower 14 bits only, not full address.
2017-03-09 11:29:51 -08:00
11c8857b5d
Don't re-read I$ RAMs on stall
2017-03-09 11:29:51 -08:00
db0a02b78e
WIP on priv-1.10
2017-03-09 11:29:51 -08:00
43dea38ee9
dcache: we need the bits within the beat so select the right word ( #575 )
...
We now have confirmation that it fixed the problem.
2017-03-08 00:19:09 -08:00
d0ae087587
rocket: allow scratchpad address to be configurable ( #570 )
2017-03-06 21:35:45 -08:00
676974281a
rocket: describe dcache scratchpad as memory
2017-03-03 02:54:48 -08:00
8e4f348dda
rocket: if no MMU, don't print it in DTS
2017-03-03 00:48:26 -08:00
4535de2669
rocket: use diplomatic interrupts
...
This makes it possible for the PLIC to work with heterogenous cores.
2017-03-02 21:19:23 -08:00
5bd9f18e5b
rocket: add dts cpu description
2017-03-02 21:19:22 -08:00
fd972f5c67
icache: back-pressure is unnecessary ( #564 )
...
* icache: back-pressure is unnecessary
* icache: require that the response arrives after the request
2017-02-24 21:01:56 -08:00
3931b0faff
coreplex: assume L1 runs no slower than L2
2017-02-17 15:15:41 +01:00
e8c8d2af71
Heterogeneous Tiles ( #550 )
...
Fundamental new features:
* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.
Additional changes that got rolled in along the way:
* rocket: Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
2017-02-09 13:59:09 -08:00
8225676a86
For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN
...
See https://github.com/riscv/riscv-isa-sim/issues/76
2017-02-02 11:55:08 -08:00
75edf42323
Set xPIE=1 on xRET
...
We were setting xPIE=0 instead. This is a benign bug, but still a bug.
2017-02-02 11:55:08 -08:00
9ca8f514c0
rocket: creating Bundles in an object also break dedup!
2017-01-31 14:45:11 -08:00
e5af59db68
rocketchip: work-around ucb-bar/chisel3#472
2017-01-31 14:20:02 -08:00
972953868c
uncore: switch to new diplomacy Node API
...
Most adapters should work on multiple ports.
This patch changes them all.
2017-01-29 15:54:45 -08:00
03f2fe02ac
coreplex: support rational crossing to L2 ( #534 )
2017-01-27 17:09:43 -08:00
5d70265e86
rocket: L1 only needs cache-line transfer sizes
2017-01-19 19:07:14 -08:00
bf7823f1c8
tilelink2: split suportsAcquire into T and B variants
2017-01-19 19:07:13 -08:00
c1b7c84f09
[rocket] bugfix: RoccExampleConfig looks up PAddrBits too early
2017-01-19 17:48:04 -08:00
307f938b88
[rocket] bugfix: fixes #517
2017-01-19 17:48:04 -08:00
74b6a8d02b
Refactor Tile to use cake pattern ( #502 )
...
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
2017-01-16 18:24:08 -08:00
71c4b000b3
Don't special-case power-of-2 replacement policy for BTB
...
PLRU wasn't implemented correctly for the BTB, since it wasn't
increasing the priority on replacement, only on usage. Regardless,
this should be a second-order effect, so using FIFO always is fine.
2017-01-11 13:21:55 -08:00
540502f96d
Convert frontend and icache to diplomacy/tl2 ( #486 )
...
* [rocket] file capitalization
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
2016-12-12 17:38:55 -08:00
020fbe8be9
diplomacy: make config.Parameters available in bundle connect()
...
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
2016-12-07 12:24:01 -08:00
915697cb09
Fix FEQ flag generation ( #479 )
...
FEQ is not a signaling comparison (i.e., qNaN is not an invalid input).
Also, minor code cleanup.
2016-12-06 11:54:29 -08:00
36fe024671
CacheName no longer needed in RoCCInterface
...
With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
2016-12-04 19:01:39 -08:00
624db2034b
Make instantiated RoCC use dcacheParams
2016-12-04 19:01:39 -08:00
b7963eca4e
copyright: ran scripts/modify-copyright
2016-11-27 22:15:43 -08:00
4146f6a792
TLB: do not access illegal addresses ( #460 )
2016-11-26 15:11:42 -08:00
1e0aca7358
dcache: the high bit of s2_req.typ is the SIGN bit (not size) ( #455 )
2016-11-25 15:26:22 -08:00
38c5af5bad
[rocket] cleanup mshr logic
2016-11-23 12:09:56 -08:00
dae6772624
factor out common cache subcomponents into uncore.util
2016-11-23 12:09:35 -08:00
c65c255815
[coreplex] TileId moved to groundtest
2016-11-23 12:08:45 -08:00
5f3fb64ef0
Per ABI, only x1 and x5 should be treated as function returns
...
We were doing so for x3 and x7, as well, which could reduce performance
for compilers that happen to perform indirect jumps via t2 (x7).
2016-11-22 12:01:05 -08:00
5fe107bb07
rocket: pass scratchpad address to block dcache
2016-11-21 21:13:26 -08:00
Andrew Waterman
Wesley W. Terpstra
Henry Cook
Andrew Waterman
Richard Xia
Megan Wachs
Zihao Yu
Colin Schmidt
Jacob Chang
Scott Johnson
Yunsup Lee
solomatnikov
Henry Cook
Schuyler Eldridge