riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman 8552c77972 Fix I$ reset regression FU-357 
Can't rely on s2 TLB response, so mask using s2_valid.
 2017-06-09 00:48:24 -07:00
Andrew Waterman 07ad9203ff Fix FMUL sign of zero 2017-06-05 17:35:42 -07:00
Andrew WatermanandWesley W. Terpstra 16ecbdd5b2 Reduce fanout on critical I$ miss signal 2017-06-02 20:45:50 -07:00
Andrew WatermanandWesley W. Terpstra 27b143013f Improve ITLB QoR 
- No need to check cacheability
- Remove a gate delay from PMP path
 2017-06-02 20:45:50 -07:00
Andrew WatermanandWesley W. Terpstra 0ffb2c8baf Simplify and improve QoR of ShiftQueue 2017-06-02 20:44:52 -07:00
Andrew WatermanandWesley W. Terpstra 8229bdee03 Remove FP unboxing from FMA critical path 2017-06-02 20:44:52 -07:00
Andrew WatermanandWesley W. Terpstra 7504b47bbe Improve code quality in FP->FP and Int->FP units 2017-06-02 20:44:52 -07:00
Andrew WatermanandWesley W. Terpstra 84c4ae775f Improve QoR for FP->Int conversions 2017-06-02 20:44:52 -07:00
Andrew WatermanandWesley W. Terpstra 07968df183 Refactor FP Classify 2017-06-02 20:44:52 -07:00
Andrew WatermanandWesley W. Terpstra 6ecd58a977 Incorporate new div/sqrt unit 2017-06-02 20:44:15 -07:00
Andrew Waterman 7eefc12705 Support vectored stvec interrupts, too 
https://github.com/riscv/riscv-isa-manual/commit/137812654e54e5d765e21909679a2a24a38be123
 2017-05-07 15:40:08 -07:00
Andrew WatermanandAndrew Waterman c6135a02df Revert "rocket: hard-wire UXL/SXL fields to 0" 
This reverts commit ea0714bfcb.

We've waffled on this matter in the priv spec: https://github.com/riscv/riscv-isa-manual/commit/326bec83de23f4d2daf24cfed6b5251748cad632
 2017-05-07 15:23:21 -07:00
Andrew WatermanandAndrew Waterman dd1546fd69 Check PPN LSBs for superpage PTEs 
https://github.com/riscv/riscv-isa-manual/commit/5a32fe87820f2f0f7ffab16a4a33906e78e26abb
 2017-05-05 15:30:09 -07:00
Andrew WatermanandYunsup Lee 398600d4da Interlock to prevent ITIM hazard when tl.a.valid & tl.d.valid & !tl.d.ready 2017-05-04 00:57:29 -07:00
Andrew Waterman fa6ecdf813 Fix RVC/uncacheable instruction memory performance bug 
9c1d126965 was an incomplete fix, so
sometimes we were requesting pipeline replays when they weren't
necessary.
 2017-05-03 17:52:06 -07:00
Andrew Waterman 3a1a37d41b Support PutPartial in ScratchpadSlavePort 2017-05-02 03:07:02 -07:00
Andrew Waterman 938b089543 Remove legacy devices that use AMOALU 
I'm going to change the AMOALU API, and so I'm removing dependent dead code.
 2017-05-02 03:05:41 -07:00
Andrew Waterman f8151ce786 Remove subword load muxing in ScratchpadSlavePort 2017-05-02 00:14:46 -07:00
Andrew Waterman 044b6ed3f9 Improve logical ops in AMOALU 
As with integer ALU, shave off some muxing.
 2017-05-02 00:14:46 -07:00
Andrew Waterman f49172b5bc ScratchpadSlavePort doesn't support byte/halfword atomics 2017-05-02 00:14:46 -07:00
Andrew WatermanandAndrew Waterman dd85d7e0a0 I$: Don't raise io.resp.valid if io.s1_kill was high previous cycle 
@solomatnikov found the bug.  It doesn't manifest in Rocket because the
Frontend masks io.resp.valid with s2_valid.
 2017-04-28 16:44:58 -07:00
Andrew Waterman 7416f2a17e Unbreak groundtest 2017-04-28 02:10:33 -07:00
Andrew Waterman 8fd5ecdff8 Set io.cpu.resp.bits.addr for MMIO loads without affecting QoR 2017-04-27 19:50:38 -07:00
Andrew Waterman 7c70aa593e Minor stylistic and QoR improvements to PLIC 2017-04-27 19:35:20 -07:00
Andrew Waterman 99de42d34c Swap order of ITIM WidthWidget and Fragmenter 
e99fa057ac accidentally reversed them
 2017-04-27 15:30:02 -07:00
Andrew Waterman 8c10caeef9 Express PMP mask generation with incrementer, not adder 
DC apparently doesn't always pick up the ((x + 1) ^ x) idiom.
Use (x + ~(x + 1)) instead.
 2017-04-27 15:16:29 -07:00
Andrew Waterman b2b4725522 Fix zero-width wire issues when ITIM is disabled 2017-04-26 22:43:00 -07:00
Andrew Waterman e23ee274f6 Size hartid field with NTiles, not XLen 2017-04-26 20:11:43 -07:00
Andrew Waterman dc753bfa95 Fix I$ elaboration when ITIM is disabled 2017-04-26 19:35:35 -07:00
Andrew Waterman 80d826b94a Make DTIM deduplicatable 2017-04-26 19:35:35 -07:00
Andrew Waterman 418879a47f Add Instruction Tightly Integrated Memory 2017-04-26 19:35:35 -07:00
Andrew Waterman ee6702e5e0 Support indexing 1-entry Seqs 
It's a zero-width wire special case.

Closes #706.
 2017-04-26 19:35:35 -07:00
Andrew Waterman 2e23d46631 Use val instead of def in ECC calculations 
This allows nicer-looking code to avoid generating lots of redundant nodes.
 2017-04-26 19:35:35 -07:00
Andrew WatermanandAndrew Waterman 65928dc6a0 Don't push RAS for "auipc ra, X; jalr ra, ra, Y" 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman 36a7971975 Bypass scoreboard to reduce MMIO latency 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman 845e6f7458 Filter out duplicate test suites 
I botched the refactoring in 5934c7b4b9
 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman f2d4cb8152 Update RAS speculatively from fetch stage 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman 3b2c15b648 Use tininess-after-rounding in FPU 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman c36c171202 Use correct interrupt priority order 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman bf861293d9 Add ShiftQueue; use it 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman d24d8ff84b Don't stall the frontend, making it easier to add more features later 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman 061a0adceb Fetch smaller parcels from the I$ 2017-04-24 02:01:15 -07:00
Andrew WatermanandAndrew Waterman 458d80cb18 For Verilator, rename +start to +dump-start to match VCS 2017-04-20 17:00:46 -07:00
Andrew WatermanandAndrew Waterman 2faf8ea239 Add +dump-start=N option to VCS 
Starts dumping waveform on cycle N.

Can control stop cycle with +max-cycles.
 2017-04-20 17:00:46 -07:00
Andrew WatermanandMegan Wachs 67404a665b When not using a cache, LR/SC isn't legal even on cacheable memory 2017-04-20 08:47:03 -07:00
Andrew WatermanandAndrew Waterman d82a0dc231 Mitigate D$ exception critical path, yet again 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman c99ce7ce5d Only report D$ exceptions on not-nacked accesses 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman 5934c7b4b9 Fix description of LR/SC test suites 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman a956b78dd2 In TLBPermissions, merge across some region types 
We only care whether they have side effects or not.
 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman 6de6f38894 Pipeline D$ exception response into s2 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman 657f4d4e0c Permit early grant acks to broadcast hub 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman cc9ec1d51a Send D$ grant acks early; accept release acks early 
We now need to block the B-channel for a few cycles after a grant to
allow the processor to get at least one request through, preventing
livelock.
 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman 728569c717 Reduce access-exception generation critical path 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman a59a3f15e4 Disable LR/SC tests for scratchpad configs 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman c366007a0d Tighten PMAs for LR/SC and misaligned accesses 
- LR/SC on cacheable memory only (not even scratchpad)
- No misaligned accesses on regions with get/put-effects
 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman 74a7838de0 In TLBPermissions, don't merge regions of different types 2017-04-18 00:47:58 -07:00
Andrew WatermanandAndrew Waterman 7871ec82c4 Guarantee probe forward progress during LR storm 2017-04-18 00:47:58 -07:00
Andrew WatermanandYunsup Lee debcbca7de Make PMP tolerant to PA size << VA size 2017-04-17 10:28:33 -07:00
Andrew WatermanandYunsup Lee a454edaaf7 Treat exceptions as steps for the purposes of single-stepping 2017-04-17 10:28:33 -07:00
Andrew WatermanandAndrew Waterman 34d45b4fb0 Fix whitespace error 2017-04-14 01:03:11 -07:00
Andrew WatermanandAndrew Waterman fdfcffb0b2 Catch bad physical address MSBs when VA size > PA size 2017-04-14 01:03:11 -07:00
Andrew WatermanandAndrew Waterman 6fbbccca3e Improve Seq indexing QoR 2017-04-14 01:03:11 -07:00
Andrew WatermanandAndrew Waterman d203c4c654 Check AMO operation legality in TLB 2017-04-14 01:03:11 -07:00
Andrew WatermanandAndrew Waterman b9e042d2bf Unconditionally write badaddr, possibly to zero 
https://github.com/riscv/riscv-isa-manual/commit/59d33f6b833d6499edfa825a204933098345d53d
 2017-04-12 13:35:02 -07:00
Andrew WatermanandAndrew Waterman 9a983c12a3 Implement new FP encoding proposal 
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
 2017-04-10 22:38:25 -07:00
Andrew WatermanandAndrew Waterman 470c6711a7 Do some CSE by hand, per @terpstra 2017-04-10 22:38:25 -07:00
Andrew WatermanandAndrew Waterman a43bf2feae Add vectored interrupt support 
https://github.com/riscv/riscv-isa-manual/commit/4dcaa944ba40e074d25516a157fc37f7491b71cc

I also added a test, which does indeed pass, but I don't want to bump
riscv-tools for that alone:

https://github.com/riscv/riscv-tests/commit/ba6d88466a96ec3147b96a57f746a137085764f9
 2017-04-08 00:29:45 -07:00
Andrew WatermanandAndrew Waterman 5c458322b5 bump chisel for withReset bugfix 2017-04-05 21:46:55 -07:00
Andrew WatermanandAndrew Waterman c861c4925e Don't signal access exceptions on invalid PTEs 
The PPN should not be interpreted in this case.
 2017-04-05 21:46:55 -07:00
Andrew WatermanandAndrew Waterman 2e09253d26 Revive I$ parity option 
Pipeline the parity check into the second stage, so that the data
RAM access + parity check do not become the critical path.
 2017-04-05 21:46:55 -07:00
Andrew WatermanandAndrew Waterman 43917dd59f Get I$ s1_kill signal off the critical path 2017-04-05 21:46:55 -07:00
Andrew WatermanandAndrew Waterman 744fb2e4b9 Cut imem.resp.ready critical path with a flow queue 
This is only necessary for RVC, where the decode latency is much higher.
 2017-04-05 21:46:55 -07:00
Andrew WatermanandAndrew Waterman 3e72f9779f Handle single-step with a pipeline stall, not a flush 
The pipeline flush approach broke when I changed the pipeline stage
the flush happens from
 2017-04-05 19:52:44 -07:00
Andrew WatermanandAndrew Waterman 19f0ae64a0 Only set id_reg_fence when AMO/FENCE is actually executed 
This is a performance bug, not a correctness bug.  But randomly stalling
because of garbage bits coming out of the I$ should be avoided.

h/t @solomatnikov
 2017-04-03 21:13:52 -07:00
Andrew WatermanandAndrew Waterman 410e9cf736 I$ bugfix, to be reworked 2017-03-31 12:17:41 -07:00
Andrew Waterman a8a2ee711c Give I$ RAMs consistent names 2017-03-30 15:50:54 -07:00
Andrew Waterman 2720095b8e Give D$ RAMs consistent names 2017-03-30 15:49:14 -07:00
Andrew Waterman 70e7e90c02 Remove splitMetadata option from L1 caches 
This is a property of the specific cache microarchitecture, not actually
an independently tunable knob.
 2017-03-30 15:48:55 -07:00
Andrew Waterman fd39eadcd6 New PMP encoding 2017-03-30 00:36:23 -07:00
Andrew Waterman 3546c8d133 If any PMPs are supported, all CSRs exist 2017-03-30 00:36:23 -07:00
Andrew Waterman 8f73a58d90 Report access exception, not page fault, if page-table walk fails 2017-03-30 00:36:23 -07:00
Andrew Waterman 25232070ec Don't redundantly set resp_ae in PTW 2017-03-30 00:36:23 -07:00
Andrew Waterman 80fb002962 Don't use Vec as lvalue 2017-03-30 00:36:23 -07:00
Andrew WatermanandAndrew Waterman 44fb3be7d0 Fix MMIO/cache refill concurrency bug in DCache 
There's a structural hazard on s2_req, so disallow cache refill initiation
while any MMIO loads are in flight.
 2017-03-28 17:16:29 -07:00
Andrew WatermanandAndrew Waterman db3ed12ce3 Fix regression in groundtest DummyPTW 
Initialize all fields in PTWResp for determinism, which should
prevent this sort of problem in the future.
 2017-03-28 00:56:14 -07:00
Andrew WatermanandAndrew Waterman 4215f480ef Write instruction to badaddr on illegal instruction traps 2017-03-28 00:56:14 -07:00
Andrew Waterman 05cbdced78 Work around zero-entry vec issue in Chisel 2017-03-27 17:57:26 -07:00
Andrew Waterman d42d8aaea7 Make SEIP writable 2017-03-27 16:37:09 -07:00
Andrew Waterman c7c357e716 Add local interrupts to core (but not yet to coreplex) 2017-03-27 16:37:09 -07:00
Andrew Waterman 069858a20c rocket: separate page faults from physical memory access exceptions 2017-03-27 16:37:09 -07:00
Andrew Waterman ea0714bfcb rocket: hard-wire UXL/SXL fields to 0 
https://github.com/riscv/riscv-isa-manual/commit/a2a3346e7345619efe3b5e8620d4a87c72d21ad0
 2017-03-27 16:37:09 -07:00
Andrew WatermanandAndrew Waterman 0e2b780089 Bump hardfloat, giving us the 5th rounding mode finally! 2017-03-26 14:20:16 -07:00
Andrew WatermanandAndrew Waterman e710e32f10 Implement new FP encoding proposal 
Single-precision values are stored in the regfile as double-precision,
so that FSD on a single-precision value stores a proper double and
FLD restores it as either a double or a single.
 2017-03-26 14:20:16 -07:00
Andrew WatermanandAndrew Waterman 7180352067 Fix groundtest to provide missing signals to TLB 2017-03-26 14:20:16 -07:00
Andrew WatermanandAndrew Waterman 5d1165c850 Express PMP mask generator using a carry chain 
This allows it to be optimized like an adder, improving QoR when it
is on the critical path.
 2017-03-26 14:20:16 -07:00
Andrew WatermanandAndrew Waterman bb42f3bf3b WIP on FPU subword recoding 2017-03-26 14:20:16 -07:00
Andrew Waterman 17b1ee3037 Default to 8 PMPs; support 0 PMPs 2017-03-24 16:39:52 -07:00
Andrew Waterman 97006ab396 Don't modulate PMP privilege on passsthrough when !usingVM 2017-03-24 16:39:52 -07:00
Andrew Waterman 3f0d2fe826 Instantiate PTW unconditionally 
This keeps the PMP datapaths intact.  The PTW itself will get optimized
away for the !usingVM case.
 2017-03-24 16:39:52 -07:00
Andrew Waterman 30415215b8 Don't check for exceptions on ScratchpadSlavePort accesses 2017-03-24 16:39:52 -07:00