Andrew Waterman
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130fa95ed6
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expand HTIF's PCR register space
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2012-07-27 14:52:39 -07:00 |
|
Andrew Waterman
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4e44ed7400
|
allow back pressure on IPI requests
|
2012-07-17 22:55:40 -07:00 |
|
Huy Vo
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fd95159837
|
INPUT/OUTPUT orderring swapped
|
2012-07-12 18:16:57 -07:00 |
|
Huy Vo
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04304fe788
|
moving util out into Chisel standard library
|
2012-06-06 12:51:26 -07:00 |
|
Andrew Waterman
|
7f6319047e
|
update to new scala/chisel/Mem
|
2012-06-06 02:47:22 -07:00 |
|
Huy Vo
|
7408c9ab69
|
removing wires
|
2012-05-24 10:42:39 -07:00 |
|
Andrew Waterman
|
a2f6d01c1b
|
add programmable coreid register
|
2012-05-09 03:09:22 -07:00 |
|
Andrew Waterman
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e0e1cd5d32
|
add IPIs and an IPI test
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
|
2012-05-08 22:58:00 -07:00 |
|
Andrew Waterman
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86d56ff67b
|
refactor cpu/i$/d$ into Tile (rather than Top)
|
2012-03-24 16:57:28 -07:00 |
|
Andrew Waterman
|
3a487ac89b
|
improve htif<->pcr interface
|
2012-03-24 16:57:28 -07:00 |
|
Andrew Waterman
|
54fa6f660d
|
new supervisor mode
|
2012-03-24 13:03:31 -07:00 |
|
Yunsup Lee
|
8c50c81b81
|
drop vec_irq_aux pcr register, now everything goes through badvaddr
|
2012-03-17 14:03:57 -07:00 |
|
Yunsup Lee
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b19d783fbd
|
add vector irq handler
|
2012-03-14 14:15:28 -07:00 |
|
Yunsup Lee
|
040d62f372
|
refactored vector exception handling interface
|
2012-03-13 23:45:34 -07:00 |
|
Yunsup Lee
|
b100544b25
|
datapath to read out vector state
|
2012-03-13 23:45:34 -07:00 |
|
Yunsup Lee
|
a1b30282dd
|
major refactoring on vector exception interface
|
2012-03-09 01:09:22 -08:00 |
|
Yunsup Lee
|
d4ec7ff4d9
|
refined vector exception interface
|
2012-03-03 16:11:54 -08:00 |
|
Yunsup Lee
|
1054cec087
|
add vec countq interface
|
2012-03-02 00:43:32 -08:00 |
|
Huy Vo
|
5b0f7ccf68
|
updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
|
2012-02-26 17:24:08 -08:00 |
|
Yunsup Lee
|
94ba32bbd3
|
change package name and sbt project name to rocket
|
2012-02-25 17:09:26 -08:00 |
|
Yunsup Lee
|
946e0c6e4e
|
add vector exception infrastructure
|
2012-02-25 16:37:56 -08:00 |
|
Andrew Waterman
|
7034c9be65
|
new htif protocol and implementation
You must update your fesvr and isasim!
|
2012-02-19 23:15:45 -08:00 |
|
Andrew Waterman
|
1b5e39e7fc
|
fix bug in BTB
a BTB update followed by a taken branch could cause incorrect control flow.
|
2012-02-15 21:36:08 -08:00 |
|
Andrew Waterman
|
725190d0ee
|
update to new chisel
|
2012-02-11 17:20:33 -08:00 |
|
Yunsup Lee
|
f47d888feb
|
vvcfgivl and vsetvl works
|
2012-02-09 02:35:21 -08:00 |
|
Andrew Waterman
|
128ec567ed
|
make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
|
2012-02-09 01:34:00 -08:00 |
|
Yunsup Lee
|
fcc8081c4d
|
hook up the vector command queue
|
2012-02-09 01:28:16 -08:00 |
|
Andrew Waterman
|
b3f6f9a5fd
|
fix BTB misprediction check for negative addresses
also index BTB with PC, not PC+4
|
2012-02-08 15:05:28 -08:00 |
|
Andrew Waterman
|
5403d069e9
|
add fp loads/stores
|
2012-02-07 23:54:25 -08:00 |
|
Andrew Waterman
|
41855a6d47
|
fix missing "otherwise" in PCR file
this fixes timer interrupts for VLSI backend.
|
2012-01-26 19:33:55 -08:00 |
|
Andrew Waterman
|
f1c355e3cd
|
check pc/effective address sign extension
|
2012-01-24 00:15:17 -08:00 |
|
Andrew Waterman
|
a5a020f97b
|
update chisel and remove SRAM_READ_LATENCY
|
2012-01-23 20:59:38 -08:00 |
|
Henry Cook
|
1d76255dc1
|
new chisel version jar and find and replace INPUT and OUTPUT
|
2012-01-18 14:39:57 -08:00 |
|
Andrew Waterman
|
0369b05deb
|
move replays to writeback stage
|
2012-01-17 21:12:31 -08:00 |
|
Andrew Waterman
|
1c8f496811
|
fix fpga build
|
2012-01-13 20:04:11 -08:00 |
|
Andrew Waterman
|
142dfc6e07
|
made tohost/fromhost 64 bits wide
|
2012-01-03 15:09:08 -08:00 |
|
Andrew Waterman
|
3045b33460
|
remove second RF write port
load miss writebacks are treated like mul/div now.
|
2012-01-02 02:51:30 -08:00 |
|
Andrew Waterman
|
2f8fcebea0
|
remove datapath register resets resets
|
2012-01-01 16:09:40 -08:00 |
|
Rimas Avizienis
|
da2fdf4f85
|
fixed console i/o
|
2011-11-30 22:51:59 -08:00 |
|
Rimas Avizienis
|
c42d8149b7
|
moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
|
2011-11-17 23:50:45 -08:00 |
|
Rimas Avizienis
|
db87924fbf
|
made eret instruction take an illegal inst exception when ET is set
|
2011-11-14 14:35:10 -08:00 |
|
Rimas Avizienis
|
cd6e463320
|
added ei and di instructions
|
2011-11-14 13:48:49 -08:00 |
|
Rimas Avizienis
|
b791010bb1
|
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
|
2011-11-14 04:13:13 -08:00 |
|
Rimas Avizienis
|
890bfa7c48
|
added IPIs and timer interrupts
|
2011-11-14 03:24:02 -08:00 |
|
Rimas Avizienis
|
5b29765917
|
synced up with supervisor mode state in latest ISA simulator
|
2011-11-14 01:37:20 -08:00 |
|
Rimas Avizienis
|
345f950eff
|
added timer interrupt support
|
2011-11-13 00:27:57 -08:00 |
|
Rimas Avizienis
|
e4fa94aa27
|
checkpoint
|
2011-11-10 17:41:22 -08:00 |
|
Rimas Avizienis
|
f86d5b1334
|
cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
|
2011-11-10 11:26:13 -08:00 |
|
Rimas Avizienis
|
4bd0263a4a
|
added misaligned instruction check, cleaned up badvaddr handling
|
2011-11-10 03:38:59 -08:00 |
|
Rimas Avizienis
|
603ede8bfe
|
access faults now write badvaddr PCR register with faulting address
|
2011-11-10 02:46:09 -08:00 |
|