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Author SHA1 Message Date
Henry CookandAndrew Waterman 3d0ed80ef6 new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels 2017-04-27 18:17:31 -07:00
Henry CookandAndrew Waterman bdb526a9f0 coreplex: DefaultCoreplex => RocketPlex 2017-04-27 18:17:09 -07:00
Henry Cook e99fa057ac cleanup scratchpad nodes 2017-04-27 14:02:05 -07:00
Henry CookandGitHub 635f119422 Merge pull request #709 from ucb-bar/bump-hardfloat 
bump hardfloat
 2017-04-26 16:47:49 -07:00
Henry Cook ebe27614d2 bump hardfloat 2017-04-26 15:37:29 -07:00
Henry CookandGitHub 0a9f632cb0 Merge pull request #708 from ucb-bar/debug_busy_data 
debug: Prevent writes to DATA/PROGBUF when busy
 2017-04-26 14:32:10 -07:00
Henry CookandGitHub 1bdb247002 Merge pull request #697 from ucb-bar/async_queue_option 
Add narrowData option to AsyncQueue.
 2017-04-25 17:43:28 -07:00
Henry CookandGitHub 7f5f1c7631 Merge branch 'master' into async_queue_option 2017-04-25 14:58:11 -07:00
Henry CookandGitHub 95591cc608 Merge pull request #704 from ucb-bar/verbose-require 
Miscellaneous uncore cleanups
 2017-04-25 14:57:58 -07:00
Henry CookandGitHub 9bb0d92381 Merge branch 'master' into async_queue_option 2017-04-25 11:23:22 -07:00
Henry Cook 60d71efa36 ahb: make hreadyout fuzzing a sram parameter 2017-04-25 11:11:31 -07:00
Henry Cook ca435c2f40 uncore: more verbose requires 2017-04-25 11:11:31 -07:00
Henry CookandWesley W. Terpstra 54820e094d Make more require statements in diplomacy verbose (#693) 
* diplomacy: add more verbose requirements
* bump firrtl
 2017-04-20 13:18:39 -07:00
Henry CookandWesley W. Terpstra ef8a819763 Miscellaneous periphery improvements (#689) 
* fifofixer: work around zero-width wires for single source id
* periphery: sourceshrinker takes maxInFlight parameter
 2017-04-20 11:28:00 -07:00
Henry CookandGitHub 9f371abf3b Merge pull request #638 from ucb-bar/riscv-tools-on-priv-1.10 
Resturn riscv-tools to the priv 1.10 branch vs the pre-merge Debug v0…
 2017-03-31 01:56:36 -07:00
Henry CookandGitHub e92eaa7156 Merge branch 'master' into riscv-tools-on-priv-1.10 2017-03-30 22:31:29 -07:00
Henry CookandGitHub e8f337e963 Merge pull request #636 from ucb-bar/name-rams 
Name L1$ RAMs consistently
 2017-03-30 22:30:12 -07:00
Henry CookandGitHub b9550e8523 Merge branch 'master' into name-rams 2017-03-30 17:36:01 -07:00
Henry CookandGitHub b6da81a66c Merge pull request #624 from ucb-bar/debug_v013_pr 
Debug v013 [WIP]
 2017-03-30 17:35:26 -07:00
Henry CookandGitHub bcaee9834c travis_wait 30 2017-03-30 13:22:33 -07:00
Henry CookandAndrew Waterman d3bc99e253 get local interrupts out of the tile 2017-03-30 00:36:23 -07:00
Henry CookandWesley W. Terpstra 996a31364a rocket: remove hard-coded paddrBits (#610) 
Fall back on global variable but check that it is compatible with memory as seen from rocket's tilelink master port.
 2017-03-24 22:30:18 -07:00
Henry CookandGitHub 797c18b8db Make some requirement failures more verbose (#608) 
* tilelink: verbose requires in xbar

* diplomacy: verbose requires
 2017-03-23 21:55:11 -07:00
Henry CookandGitHub 055b8ba1f0 rocket: avoid LinkedHashMap.keys to preserve traversal order (#603) 2017-03-22 14:38:33 -07:00
Henry CookandGitHub 4f5f686c7e bump riscv-tools (#586) 2017-03-15 18:09:26 -07:00
Henry CookandGitHub e9c694522b Merge pull request #578 from ucb-bar/priv-1.10 
Privileged architecture updates
 2017-03-14 13:20:19 -07:00
Henry CookandGitHub bb0390630c Merge branch 'master' into priv-1.10 2017-03-13 21:40:12 -07:00
Henry CookandGitHub 4eb261c895 Merge pull request #582 from ucb-bar/more-fuzzing 
Fuzzer enhancements
 2017-03-13 15:31:51 -07:00
Henry Cook fe287864ef bump firrtl 2017-03-13 13:14:16 -07:00
Henry CookandGitHub 1a3fec61c0 Merge branch 'master' into priv-1.10 2017-03-13 11:59:18 -07:00
Henry CookandAndrew Waterman dbc8f4b30b last => done 2017-03-10 15:58:38 -08:00
Henry CookandWesley W. Terpstra 4af437fdab RANDOMIZE_MEM_INIT vlsi_mem_gen (#572) 2017-03-07 01:56:15 -08:00
Henry CookandGitHub d0ae087587 rocket: allow scratchpad address to be configurable (#570) 2017-03-06 21:35:45 -08:00
Henry CookandGitHub 229fb2251d coreplex: hack to fix tile dedup (#569) 2017-03-06 16:36:03 -08:00
Henry CookandGitHub 33ffb62326 Merge pull request #568 from ucb-bar/elide-empty-int-ext 
PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0
 2017-03-03 12:46:11 -08:00
Henry CookandGitHub 3a55a1afae Merge pull request #562 from ucb-bar/periphery-adjustments 
Periphery adjustments
 2017-03-02 11:14:07 -08:00
Henry Cook 9544b8007e bump chisel3 2017-03-02 10:41:26 -08:00
Henry Cook 9ce6898d46 firrtl: bump firrtl 2017-03-01 16:58:29 -08:00
Henry CookandGitHub 42cc61a80c Merge branch 'master' into periphery-adjustments 2017-03-01 16:38:51 -08:00
Henry Cook 9bfcb40cb4 util: Majority on sets of bools 2017-02-27 20:18:28 -08:00
Henry Cook 6958f05a85 Merge remote-tracking branch 'origin/master' into periphery-adjustments 2017-02-27 19:40:55 -08:00
Henry CookandGitHub 62f5727bc6 periphery: peripheryBusBytes and socBusBytes 2017-02-27 19:19:41 -08:00
Henry CookandGitHub 35877e6ec1 Merge branch 'master' into periphery-adjustments 2017-02-24 10:37:41 -08:00
Henry Cook a281ad8ad2 rocketchip: rename some periphery ports 2017-02-23 18:28:04 -08:00
Henry Cook 6c3011d513 periphery: make external interrupts a UInt rather than a Vec[Bool] 2017-02-23 18:27:44 -08:00
Henry CookandGitHub 027d6247b6 diplomacy: silence a warning (#560) 2017-02-22 11:28:04 -08:00
Henry CookandGitHub e8c8d2af71 Heterogeneous Tiles (#550) 
Fundamental new features:

* Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces.
* Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile.
* Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile.
* Defined RocketCoreParams: All the parameters that can be varied per-core.
* Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes.
* Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created.
* Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little.
* Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support.

Additional changes that got rolled in along the way:

* rocket: 	Fix critical path through BTB for I$ index bits > pgIdxBits
* coreplex: tiles connected via :=*
* groundtest: updated to use TileParams
* tilelink: cache cork requirements are relaxed to allow more cacheless masters
 2017-02-09 13:59:09 -08:00
Henry CookandGitHub f9acd4988c Merge pull request #551 from edwardcwang/configdoc 
Update config override documentation
 2017-02-09 11:56:38 -08:00
Henry CookandGitHub fc7838ff7b Merge branch 'master' into configdoc 2017-02-09 10:09:30 -08:00
Henry CookandGitHub fbefbb5549 Merge pull request #552 from ucb-bar/fix-abs-func 
Fix up Absolute value.
 2017-02-09 10:09:16 -08:00
Henry CookandGitHub b567a2a356 Merge pull request #536 from ucb-bar/diplomacy-star-nodes 
diplomacy: add :*= and :=* to support flexible # of edges
 2017-01-30 11:19:33 -08:00
Henry CookandGitHub 0fe2899c74 [tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit (#528) 2017-01-25 12:10:49 -08:00
Henry Cook e03ba637f4 [regression] remove FancyMemTest (timing out) 2017-01-19 17:48:04 -08:00
Henry Cook c1b7c84f09 [rocket] bugfix: RoccExampleConfig looks up PAddrBits too early 2017-01-19 17:48:04 -08:00
Henry Cook e0411c6cde [coreplex] bugfix: re-enable multicore configs via WithNCores 2017-01-19 17:48:04 -08:00
Henry Cook 307f938b88 [rocket] bugfix: fixes #517 2017-01-19 17:48:04 -08:00
Henry CookandGitHub 1b31dfa700 Update sbt to 13.12 (#514) 
Closes #496
 2017-01-17 16:26:22 -08:00
Henry CookandGitHub 9a6634cd40 Add TLBuffers on the L1 backends and blind exit points (#513) 
* [coreplex] add TLBuffers on the exit points from the Tile and Coreplex
* [config] WithBootROMFile
 2017-01-17 11:57:23 -08:00
Henry CookandGitHub 74b6a8d02b Refactor Tile to use cake pattern (#502) 
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
 2017-01-16 18:24:08 -08:00
Henry Cook a8ee7e0678 Update README 2016-11-28 16:10:50 -08:00
Henry Cook 86065e5fb8 Merge remote-tracking branch 'origin/master' into bump-submodules 2016-11-28 13:49:59 -08:00
Henry Cook 837d207064 [travis] split up groundtest into two suites 2016-11-23 12:27:40 -08:00
Henry Cook 38c5af5bad [rocket] cleanup mshr logic 2016-11-23 12:09:56 -08:00
Henry Cook dae6772624 factor out common cache subcomponents into uncore.util 2016-11-23 12:09:35 -08:00
Henry Cook 16d0f522b0 [tracegen] filter seed report 2016-11-23 12:09:09 -08:00
Henry Cook c65c255815 [coreplex] TileId moved to groundtest 2016-11-23 12:08:45 -08:00
Henry Cook 28c6be90ab [rocket] require refillcycesperbeat == 1 and remove flowthroughserializer 2016-11-20 19:36:51 -08:00
Henry Cook ff9b5bf8fc [rocket] nbdcache release bugfix 2016-11-20 19:07:06 -08:00
Henry Cook e68795421a remove L2 regressions for now 2016-11-19 20:11:20 -08:00
Henry Cook 3f47d5b5eb [rocket] re-enable working NBDcache (passes Tracegen) 2016-11-19 19:19:16 -08:00
Henry Cook c31b41a7ac [tl2] add grant finisher comment 2016-11-19 19:16:43 -08:00
Henry Cook 2976fd84e4 [rocket] resolve cde/config conflicts 2016-11-18 19:11:34 -08:00
Henry Cook 8b908465e0 [tl2] convert NBDcache to TL2 (WIP; compiles but untested) 2016-11-18 19:04:06 -08:00
Henry Cook 5f1cc19d71 [tl2] fix comment explaining permissions 2016-11-18 19:02:17 -08:00
Henry Cook 10112da4e7 [tl2] won't need putthrough opcode 2016-11-18 19:02:17 -08:00
Henry Cook 5bd343bac8 [rocket] d_last && d.fire() => d_done 2016-11-17 18:42:59 -08:00
Henry Cook 1ddccb1b33 [rocket] add TODO for single cycle ack 2016-11-17 18:42:59 -08:00
Henry Cook 94086f2270 [tl2] broadcast hub probe port width bugfix 2016-11-17 18:42:59 -08:00
Henry Cook 960c2723ab [tl2] MemoryOpCategories: use def to supply Cat'd consts 2016-11-17 18:42:59 -08:00
Henry Cook 92e233d596 [groundtest] testramaddr constant in package 2016-11-16 18:42:56 -08:00
Henry Cook e1992d7c55 [rocket] grant addr bugfix 2016-11-16 18:12:06 -08:00
Henry Cook 84f249bd03 [rocketchip] BigInt cast 2016-11-16 18:11:06 -08:00
Henry Cook da7ecfd189 [rocket] probeack vs probeackdata bugfix 2016-11-16 17:27:02 -08:00
Henry Cook 75d4347192 [groundtest] runs tests with new coreplex and top 2016-11-16 17:05:53 -08:00
Henry Cook 24e3216fcf coreplex: allow zero interrupt sink/sources 2016-11-16 16:50:36 -08:00
Henry Cook 479bc82f03 tilelink2 Broadcast: improve bufferless throughput 2016-11-16 16:50:36 -08:00
Henry Cook 408e78e35e rocketchip Periphery: ExtMem and ExtBus Configs 2016-11-16 16:50:30 -08:00
Henry Cook 1f51564577 [rocket] dcache probe ack data bugfix 2016-11-16 14:25:21 -08:00
Henry Cook 66a2c5544e [rocket] L1D acquire addr bugfix 2016-11-16 13:38:52 -08:00
Henry Cook c5e03c9c76 [rocket] dcache release addr bugfix 2016-11-16 13:14:51 -08:00
Henry Cook 2d68f12115 [tl2] give groundtest tile some output nodes 2016-11-14 18:09:40 -08:00
Henry Cook 0e30364f56 WIP 2016-11-14 13:39:01 -08:00
Henry Cook c0efd247b0 [tl2] expand firstlast api and L1WB bugfix 2016-11-14 12:12:31 -08:00
Henry Cook b7730d66f2 WIP bugfixes: run until corrupted WB data (beats repeated) 2016-11-11 18:34:48 -08:00
Henry Cook 71315d5cf5 WIP scala compile and firrtl elaborate; monitor error 2016-11-11 13:07:45 -08:00
Henry Cook afa1a6d549 WIP uncore and rocket changes compile 2016-11-10 15:57:29 -08:00
Henry CookandHenry Cook 7bca99a27a [tilelink2] Add unit test configs to regression 2016-09-28 18:02:04 -07:00
Henry CookandHenry Cook 32f3f94882 [tilelink2] Fix zero-width wires in RAMModel. 2016-09-28 18:02:04 -07:00
Henry CookandHenry Cook 69e121260e [tilelink2] Add unit tests for many TL2 components 
These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.
 2016-09-28 18:02:04 -07:00
Henry Cook 1e54820f8c Merge remote-tracking branch 'origin/master' into unittest-config 2016-09-22 16:03:51 -07:00