periphery: make external interrupts a UInt rather than a Vec[Bool]

src/main/scala/rocketchip/Periphery.scala

@@ -48,7 +48,8 @@ trait HasPeripheryParameters {
 trait PeripheryExtInterrupts {
   this: TopNetwork =>
 
-  val extInterrupts = IntBlindInputNode(p(NExtTopInterrupts))
+  val nExtInterrupts = p(NExtTopInterrupts)
+  val extInterrupts = IntInternalInputNode(nExtInterrupts)
   val extInterruptXing = LazyModule(new IntXing)
 
   intBus.intnode := extInterruptXing.intnode
@@ -59,7 +60,7 @@ trait PeripheryExtInterruptsBundle {
   this: TopNetworkBundle {
     val outer: PeripheryExtInterrupts
   } =>
-  val interrupts = outer.extInterrupts.bundleIn
+  val interrupts = UInt(INPUT, width = outer.nExtInterrupts)
 }
 
 trait PeripheryExtInterruptsModule {
@@ -67,6 +68,7 @@ trait PeripheryExtInterruptsModule {
     val outer: PeripheryExtInterrupts
     val io: PeripheryExtInterruptsBundle
   } =>
+  outer.extInterrupts.bundleIn(0).zipWithIndex.foreach { case(o, i) => o := io.interrupts(i) }
 }
 
 /////

src/main/scala/rocketchip/TestHarness.scala

@@ -15,8 +15,7 @@ class TestHarness()(implicit p: Parameters) extends Module {
   }
   val dut = Module(LazyModule(new ExampleRocketTop).module)
 
-  for (int <- dut.io.interrupts(0))
-    int := Bool(false)
+  dut.io.interrupts := UInt(0)
 
   val channels = p(coreplex.BankedL2Config).nMemoryChannels
   if (channels > 0) Module(LazyModule(new SimAXIMem(channels)).module).io.axi4 <> dut.io.mem_axi4