riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

[groundtest] testramaddr constant in package

Browse Source
This commit is contained in:
Henry Cook 2016-11-16 18:42:56 -08:00
parent e1992d7c55
commit 92e233d596
3 changed files with 5 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/groundtest/Coreplex.scala
View File

@ -22,7 +22,7 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
l1tol2.node := lm.uncachedOut
}
val cbusRAM = LazyModule(new TLRAM(AddressSet(0x10000, 0xffff), false, cbus_beatBytes))
val cbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, cbus_beatBytes))
cbusRAM.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))

3
src/main/scala/groundtest/Package.scala Normal file
View File

@ -0,0 +1,3 @@
package object groundtest {
val testRamAddr = 0x10000
}

2
src/main/scala/groundtest/Regression.scala
View File

@ -72,7 +72,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
io.mem.grant.ready := Bool(true)
io.cache.req.valid := !get_sent && started
io.cache.req.bits.addr := UInt(addrMap("TL2:bootrom").start)
io.cache.req.bits.addr := UInt(testRamAddr)
io.cache.req.bits.typ := MT_WU
io.cache.req.bits.cmd := M_XRD
io.cache.req.bits.tag := UInt(0)