last => done

src/main/scala/rocket/DCache.scala

@@ -505,6 +505,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   }
 
   // performance events
-  io.cpu.acquire := edge.last(tl_out.a)
-  io.cpu.release := edge.last(tl_out.c)
+  io.cpu.acquire := edge.done(tl_out.a)
+  io.cpu.release := edge.done(tl_out.c)
 }

src/main/scala/rocket/Frontend.scala

@@ -155,7 +155,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
   io.cpu.resp.bits.btb.bits := s2_btb_resp_bits
 
   // performance events
-  io.cpu.acquire := edge.last(icache.io.mem(0).a)
+  io.cpu.acquire := edge.done(icache.io.mem(0).a)
 }
 
 /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */

src/main/scala/rocket/NBDcache.scala

@@ -975,6 +975,6 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
   io.cpu.replay_next := (s1_replay && s1_read) || mshrs.io.replay_next
 
   // performance events
-  io.cpu.acquire := edge.last(tl_out.a)
-  io.cpu.release := edge.last(tl_out.c)
+  io.cpu.acquire := edge.done(tl_out.a)
+  io.cpu.release := edge.done(tl_out.c)
 }

src/main/scala/uncore/tilelink2/Edges.scala

@@ -224,6 +224,10 @@ class TLEdge(
   def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire())
   def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
 
+  def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
+  def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire())
+  def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
+
   def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
     val r = firstlastHelper(bits, fire)
     (r._1, r._2, r._3)