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WIP scala compile and firrtl elaborate; monitor error

This commit is contained in:
Henry Cook 2016-11-11 13:07:45 -08:00
parent afa1a6d549
commit 71315d5cf5
10 changed files with 136 additions and 158 deletions
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82
src/main/scala/coreplex/BaseCoreplex.scala
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@ -24,15 +24,12 @@ case object NTrackersPerBank extends Field[Int]
case object BankIdLSB extends Field[Int]
/** Function for building some kind of coherence manager agent */
case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
/** Function for building some kind of tile connected to a reset signal */
case object BuildTiles extends Field[Seq[Parameters => LazyTile]]
/** The file to read the BootROM contents from */
case object BootROMFile extends Field[String]
trait HasCoreplexParameters {
implicit val p: Parameters
lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
lazy val lsb = p(BankIdLSB)
lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
lazy val outerMemParams = p.alterPartial({ case TLId => "L2toMC" })
lazy val outerMMIOParams = p.alterPartial({ case TLId => "L2toMMIO" })
@ -138,19 +135,11 @@ trait BankedL2CoherenceManagersModule {
trait CoreplexRISCVPlatform {
this: CoreplexNetwork =>
// Build a set of Tiles
val lazyTiles = p(BuildTiles) map { _(p) }
val legacy = LazyModule(new TLLegacy()(outerMMIOParams))
val tileIntNodes = lazyTiles.map { _ => IntInternalOutputNode() } // this should be moved into the Tile...
val lazyTiles = List.tabulate(p(NTiles)){ i => LazyModule(new RocketTile(i)) }
val debug = LazyModule(new TLDebugModule())
val plic = LazyModule(new TLPLIC(hasSupervisor, maxPriorities = 7))
val clint = LazyModule(new CoreplexLocalInterrupter)
// Kill this once we move TL2 into rocket
l1tol2.node :=
TLHintHandler()(
legacy.node)
val tileIntNodes = lazyTiles.map { _ => IntInternalOutputNode() } // this should be moved into the Tile...
debug.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
plic.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
@ -179,7 +168,11 @@ trait CoreplexRISCVPlatformModule {
} =>
val tiles = outer.lazyTiles.map(_.module)
val uncoreTileIOs = (tiles zipWithIndex) map { case (tile, i) => Wire(tile.io) }
// Remaining external coreplex signals
outer.debug.module.io.db <> io.debug
outer.clint.module.io.rtcTick := io.rtcTick
io.success := Bool(false) // Coreplex doesn't know when to stop running
println("\nGenerated Address Map")
for (entry <- p(rocketchip.GlobalAddrMap).flatten) {
@ -202,67 +195,6 @@ trait CoreplexRISCVPlatformModule {
ConfigStringOutput.contents = Some(configString)
}
println(s"\nGenerated Configuration String\n${ConfigStringOutput.contents.get}")
val nCachedPorts = tiles.map(tile => tile.io.cached.size).reduce(_ + _)
val nUncachedPorts = tiles.map(tile => tile.io.uncached.size).reduce(_ + _)
val nBanks = nMemChannels * nBanksPerMemChannel
buildUncore(p.alterPartial({
case HastiId => "TL"
case TLId => "L1toL2"
case NCachedTileLinkPorts => nCachedPorts
case NUncachedTileLinkPorts => nUncachedPorts
}))
def buildUncore(implicit p: Parameters) {
// Create a simple L1toL2 NoC between the tiles and the banks of outer memory
// Cached ports are first in client list, making sharerToClientId just an indentity function
// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
def sharerToClientId(sharerId: UInt) = sharerId
def addrToBank(addr: UInt): UInt = UInt(nBanks)
val l1tol2net = Module(new PortedTileLinkCrossbar(addrToBank, sharerToClientId))
// Create point(s) of coherence serialization
val managerEndpoints = List.tabulate(nBanks){id => p(BuildL2CoherenceManager)(id, p)}
managerEndpoints.flatMap(_.incoherent).foreach(_ := Bool(false))
val mmioManager = Module(new MMIOTileLinkManager()(p.alterPartial({
case TLId => "L1toL2"
case InnerTLId => "L1toL2"
case OuterTLId => "L2toMMIO"
})))
// Wire the tiles to the TileLink client ports of the L1toL2 network,
// and coherence manager(s) to the other side
l1tol2net.io.clients_cached <> uncoreTileIOs.map(_.cached).flatten
l1tol2net.io.clients_uncached <> uncoreTileIOs.map(_.uncached).flatten ++ io.slave
l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
outer.legacy.module.io.legacy <> mmioManager.io.outer
val mem_ic = Module(new TileLinkMemoryInterconnect(nBanksPerMemChannel, nMemChannels)(outerMemParams))
val backendBuffering = TileLinkDepths(0,0,0,0,0)
for ((bank, icPort) <- managerEndpoints zip mem_ic.io.in) {
val enqueued = TileLinkEnqueuer(bank.outerTL, backendBuffering)
icPort <> TileLinkIOUnwrapper(enqueued)
}
}
// connect coreplex-internal interrupts to tiles
for ((tile, i) <- (uncoreTileIOs zipWithIndex)) {
tile.hartid := UInt(i)
tile.resetVector := io.resetVector
tile.interrupts := outer.clint.module.io.tiles(i)
tile.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
tile.interrupts.meip := outer.tileIntNodes(i).bundleOut(0)(0)
tile.interrupts.seip.foreach(_ := outer.tileIntNodes(i).bundleOut(0)(1))
}
outer.debug.module.io.db <> io.debug
outer.clint.module.io.rtcTick := io.rtcTick
// Coreplex doesn't know when to stop running
io.success := Bool(false)
}
abstract class BaseCoreplex(implicit p: Parameters) extends BareCoreplex

17
src/main/scala/coreplex/Configs.scala
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@ -66,18 +66,7 @@ class BaseCoreplexConfig extends Config (
Module(new L2BroadcastHub()(p.alterPartial({
case InnerTLId => "L1toL2"
case OuterTLId => "L2toMC" })))
case NCachedTileLinkPorts => 1
case NUncachedTileLinkPorts => 1
//Tile Constants
case BuildTiles => {
List.tabulate(site(NTiles)){ i => (p: Parameters) =>
LazyModule(new RocketTile()(p.alterPartial({
case TileId => i
case TLId => "L1toL2"
case NUncachedTileLinkPorts => 1 + site(RoccNMemChannels)
})))
}
}
case BuildRoCC => Nil
case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
case RoccNPTWPorts => site(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
@ -108,14 +97,14 @@ class BaseCoreplexConfig extends Config (
case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
log2Up(site(TLKey(site(TLId))).nClients)
case TLKey("L1toL2") => {
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
val useMEI = site(NTiles) <= 1
TileLinkParameters(
coherencePolicy = (
if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
else new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = site(NCoreplexExtClients) + site(NUncachedTileLinkPorts),
nCachingClients = 1,
nCachelessClients = site(NCoreplexExtClients) + 1,
maxClientXacts = max_int(
// L1 cache
site(DCacheKey).nMSHRs + 1 /* IOMSHR */,

94
src/main/scala/coreplex/Coreplex.scala
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@ -22,23 +22,28 @@ trait BroadcastL2 {
trait DirectConnection {
this: CoreplexNetwork with CoreplexRISCVPlatform =>
lazyTiles.map(_.slave).flatten.foreach { scratch => scratch := cbus.node }
lazyTiles foreach { t =>
t.slaveNode.foreach { _ := cbus.node }
l1tol2.node := TLBuffer(1,1,2,2,0)(TLHintHandler()(t.cachedOut))
l1tol2.node := TLBuffer(1,0,0,2,0)(TLHintHandler()(t.uncachedOut))
}
}
trait DirectConnectionModule {
this: CoreplexNetworkModule with CoreplexRISCVPlatformModule =>
this: CoreplexNetworkModule with CoreplexRISCVPlatformModule {
val outer: CoreplexNetwork with CoreplexRISCVPlatform
val io: CoreplexRISCVPlatformBundle
} =>
val tlBuffering = TileLinkDepths(1,1,2,2,0)
val ultBuffering = UncachedTileLinkDepths(1,2)
(tiles zip uncoreTileIOs) foreach { case (tile, uncore) =>
(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, tlBuffering) }
(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> TileLinkEnqueuer(t, ultBuffering) }
tile.io.interrupts <> uncore.interrupts
tile.io.hartid := uncore.hartid
tile.io.resetVector := uncore.resetVector
// connect coreplex-internal interrupts to tiles
tiles.zipWithIndex.foreach { case (tile, i) =>
tile.io.hartid := UInt(i)
tile.io.resetVector := io.resetVector
tile.io.interrupts := outer.clint.module.io.tiles(i)
tile.io.interrupts.debug := outer.debug.module.io.debugInterrupts(i)
tile.io.interrupts.meip := outer.tileIntNodes(i).bundleOut(0)(0)
tile.io.interrupts.seip.foreach(_ := outer.tileIntNodes(i).bundleOut(0)(1))
}
}
@ -57,12 +62,24 @@ class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L
trait AsyncConnection {
this: CoreplexNetwork with CoreplexRISCVPlatform =>
val crossings = lazyTiles.map(_.slave).map(_.map { scratch =>
val crossing = LazyModule(new TLAsyncCrossing)
crossing.node := cbus.node
val monitor = (scratch := crossing.node)
(crossing, monitor)
})
val masterCrossings = lazyTiles.map { t =>
t.masterNodes map { m =>
val crossing = LazyModule(new TLAsyncCrossing)
crossing.node := m
val monitor = (cbus.node := crossing.node)
(crossing, monitor)
}
}
val slaveCrossings = lazyTiles.map { t =>
t.slaveNode map { s =>
val crossing = LazyModule(new TLAsyncCrossing)
crossing.node := cbus.node
val monitor = (s := crossing.node)
(crossing, monitor)
}
}
}
trait AsyncConnectionBundle {
@ -75,11 +92,24 @@ trait AsyncConnectionBundle {
trait AsyncConnectionModule {
this: Module with CoreplexNetworkModule with CoreplexRISCVPlatformModule {
val outer: AsyncConnection
val io: AsyncConnectionBundle
val outer: AsyncConnection with CoreplexNetwork with CoreplexRISCVPlatform
val io: AsyncConnectionBundle with CoreplexNetworkBundle with CoreplexRISCVPlatformBundle
} =>
(outer.crossings zip io.tcrs) foreach { case (slaves, tcr) =>
(outer.masterCrossings zip io.tcrs) foreach { case (masters, tcr) =>
masters.foreach { case (crossing, monitor) =>
crossing.module.io.out_clock := clock
crossing.module.io.out_reset := reset
crossing.module.io.in_clock := tcr.clock
crossing.module.io.in_reset := tcr.reset
monitor.foreach { m =>
m.module.clock := clock
m.module.reset := reset
}
}
}
(outer.slaveCrossings zip io.tcrs) foreach { case (slaves, tcr) =>
slaves.foreach { case (crossing, monitor) =>
crossing.module.io.in_clock := clock
crossing.module.io.in_reset := reset
@ -92,23 +122,19 @@ trait AsyncConnectionModule {
}
}
(tiles, uncoreTileIOs, io.tcrs).zipped foreach { case (tile, uncore, tcr) =>
(tiles.zipWithIndex, io.tcrs).zipped.foreach { case ((tile, i), tcr) =>
tile.clock := tcr.clock
tile.reset := tcr.reset
(uncore.cached zip tile.io.cached) foreach { case (u, t) => u <> AsyncTileLinkFrom(tcr.clock, tcr.reset, t) }
(uncore.uncached zip tile.io.uncached) foreach { case (u, t) => u <> AsyncUTileLinkFrom(tcr.clock, tcr.reset, t) }
val ti = tile.io.interrupts
val ui = uncore.interrupts
ti.debug := LevelSyncTo(tcr.clock, ui.debug)
ti.mtip := LevelSyncTo(tcr.clock, ui.mtip)
ti.msip := LevelSyncTo(tcr.clock, ui.msip)
ti.meip := LevelSyncTo(tcr.clock, ui.meip)
ti.seip.foreach { _ := LevelSyncTo(tcr.clock, ui.seip.get) }
ti.debug := LevelSyncTo(tcr.clock, outer.debug.module.io.debugInterrupts(i))
ti.mtip := LevelSyncTo(tcr.clock, outer.clint.module.io.tiles(i).mtip)
ti.msip := LevelSyncTo(tcr.clock, outer.clint.module.io.tiles(i).msip)
ti.meip := LevelSyncTo(tcr.clock, outer.tileIntNodes(i).bundleOut(0)(0))
ti.seip.foreach { _ := LevelSyncTo(tcr.clock, outer.tileIntNodes(i).bundleOut(0)(1)) }
tile.io.hartid := uncore.hartid
tile.io.resetVector := uncore.resetVector
tile.io.hartid := UInt(i)
tile.io.resetVector := io.resetVector
}
}

19
src/main/scala/groundtest/Configs.scala
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@ -73,15 +73,15 @@ class Edge32BitMemtestConfig extends Config(
class WithGroundTest extends Config(
(pname, site, here) => pname match {
case TLKey("L1toL2") => {
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
val useMEI = site(NTiles) <= 1
val dataBeats = (8 * site(CacheBlockBytes)) / site(XLen)
TileLinkParameters(
coherencePolicy = (
if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
else new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = site(NCoreplexExtClients) + site(NUncachedTileLinkPorts),
nCachingClients = 1,
nCachelessClients = site(NCoreplexExtClients) + 1,
maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +:
site(GroundTestKey).map(_.maxXacts))
.reduce(max(_, _)),
@ -90,19 +90,6 @@ class WithGroundTest extends Config(
dataBeats = dataBeats,
dataBits = site(CacheBlockBytes)*8)
}
case BuildTiles => {
(0 until site(NTiles)).map { i =>
val tileSettings = site(GroundTestKey)(i)
(p: Parameters) => {
LazyModule(new GroundTestTile()(p.alterPartial({
case TLId => "L1toL2"
case TileId => i
case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0
case NUncachedTileLinkPorts => tileSettings.uncached
})))
}
}
}
case BuildExampleTop =>
(p: Parameters) => LazyModule(new ExampleTopWithTestRAM(new GroundTestCoreplex()(_))(p))
case FPUKey => None

14
src/main/scala/groundtest/Coreplex.scala
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@ -1,12 +1,22 @@
package groundtest
import Chisel._
import cde.{Parameters}
import cde.Parameters
import diplomacy._
import coreplex._
import uncore.devices.NTiles
import rocket.TileId
import uncore.tilelink.TLId
class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
with BroadcastL2
with DirectConnection {
val tiles = (0 until p(NTiles)).map { i =>
LazyModule(new GroundTestTile()(p.alterPartial({
case TLId => "L1toL2"
case TileId => i
})))
}
override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))
}
@ -14,5 +24,5 @@ class GroundTestCoreplexBundle[+L <: GroundTestCoreplex](_outer: L) extends Base
class GroundTestCoreplexModule[+L <: GroundTestCoreplex, +B <: GroundTestCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
with DirectConnectionModule {
io.success := tiles.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
io.success := outer.tiles.flatMap(_.module.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
}

29
src/main/scala/rocket/dcache.scala
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@ -42,7 +42,9 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
class DCache(maxUncachedInFlight: Int = 2)(implicit val p: Parameters) extends LazyModule with HasL1HellaCacheParameters {
val node = TLClientNode(TLClientParameters(supportsProbe = TransferSizes(cacheBlockBytes)))
val node = TLClientNode(TLClientParameters(
sourceId = IdRange(0, maxUncachedInFlight),
supportsProbe = TransferSizes(cacheBlockBytes)))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
@ -54,12 +56,31 @@ class DCache(maxUncachedInFlight: Int = 2)(implicit val p: Parameters) extends L
val edge = node.edgesOut(0)
val tl_out = io.mem(0)
val grantackq = Module(new Queue(tl_out.e.bits,1))
/* TODO
edge.manager.managers.foreach { m =>
// If a slave supports read at all, it must support all TL Legacy requires
if (m.supportsGet) {
require (m.supportsGet.contains(TransferSizes(1, tlDataBytes)))
require (m.supportsGet.contains(TransferSizes(tlDataBeats * tlDataBytes)))
}
// Likewise, any put support must mean full put support
if (m.supportsPutPartial) {
require (m.supportsPutPartial.contains(TransferSizes(1, tlDataBytes)))
require (m.supportsPutPartial.contains(TransferSizes(tlDataBeats * tlDataBytes)))
}
// Any atomic support => must support 32-bit size
if (m.supportsArithmetic) { require (m.supportsArithmetic.contains(TransferSizes(4))) }
if (m.supportsLogical) { require (m.supportsLogical .contains(TransferSizes(4))) }
// We straight-up require Acquire support, this is a cache afterall?
require (edge.manager.anySupportsAcquire)
}
*/
require(rowBits == encRowBits) // no ECC
require(refillCyclesPerBeat == 1)
require(rowBits >= coreDataBits)
val grantackq = Module(new Queue(tl_out.e.bits,1))
// tags
val replacer = p(Replacer)()
def onReset = L1Metadata(UInt(0), ClientMetadata.onReset)
@ -132,7 +153,7 @@ class DCache(maxUncachedInFlight: Int = 2)(implicit val p: Parameters) extends L
require(nWays == 1)
metaWriteArb.io.out.ready := true
metaReadArb.io.out.ready := !metaWriteArb.io.out.valid
val inScratchpad = addrMap(s"TL2:dmem${tileId}").containsAddress(s1_paddr)
val inScratchpad = addrMap(s"TL2:dmem${p(TileId)}").containsAddress(s1_paddr)
val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset)
(inScratchpad, hitState, L1Metadata(UInt(0), ClientMetadata.onReset))
} else {

5
src/main/scala/rocket/nbdcache.scala
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@ -73,14 +73,14 @@ trait HasMissInfo extends HasL1HellaCacheParameters {
val way_en = Bits(width = nWays)
}
class HellaCacheReqInternal(implicit p: Parameters) extends L1HellaCacheBundle()(p)
class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreMemOp {
val phys = Bool()
}
class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData
class HellaCacheResp(implicit p: Parameters) extends L1HellaCacheBundle()(p)
class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreMemOp
with HasCoreData {
val replay = Bool()
@ -1245,6 +1245,7 @@ class SimpleHellaCacheIF(implicit p: Parameters) extends Module
object HellaCache {
def apply(cfg: DCacheConfig)(implicit p: Parameters) = LazyModule(new DCache)
// TODO convert non-blocking cache
// if (cfg.nMSHRs == 0) Module(new DCache()).io
// else Module(new HellaCache(cfg)).io
}

2
src/main/scala/rocket/rocket.scala
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@ -75,8 +75,6 @@ trait HasCoreParameters extends HasAddrMapParameters {
val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
val coreMaxAddrBits = paddrBits max vaddrBitsExtended
val nCustomMrwCsrs = p(NCustomMRWCSRs)
val nCores = p(NTiles)
val tileId = p(TileId)
// fetchWidth doubled, but coreInstBytes halved, for RVC
val decodeWidth = fetchWidth / (if (usingCompressed) 2 else 1)

30
src/main/scala/rocket/tile.scala
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@ -23,21 +23,35 @@ case class RoccParameters(
nPTWPorts : Int = 0,
useFPU: Boolean = false)
class RocketTile(implicit p: Parameters) extends LazyModule {
val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
val icacheParams = p.alterPartial({ case CacheName => "L1I" })
class RocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
val dcacheParams = p.alterPartial({
case CacheName => "L1D"
case TLId => "L1toL2"
case TileId => tileId // TODO using this messes with Heirarchical P&R
})
val icacheParams = p.alterPartial({
case CacheName => "L1I"
case TLId => "L1toL2"
})
//TODO val intNode = IntInputNode()
val slaveNode = if (p(DataScratchpadSize) == 0) None else Some(TLInputNode())
val scratch = if (p(DataScratchpadSize) == 0) None else Some(LazyModule(new ScratchpadSlavePort()(dcacheParams)))
val dcache = HellaCache(p(DCacheKey))(dcacheParams)
val ucLegacy = LazyModule(new TLLegacy()(p))
val ucLegacy = LazyModule(new TLLegacy()(icacheParams))
val cachedOut = TLOutputNode()
val uncachedOut = TLOutputNode()
cachedOut := dcache.node
uncachedOut := ucLegacy.node
val masterNodes = List(cachedOut, uncachedOut)
(slaveNode zip scratch) foreach { case (node, lm) => lm.node := TLFragmenter(p(XLen)/8, p(CacheBlockBytes))(node) }
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
val cached = dcache.node.bundleOut
val uncached = ucLegacy.node.bundleOut
val cached = cachedOut.bundleOut
val uncached = uncachedOut.bundleOut
val slave = slaveNode.map(_.bundleIn)
val hartid = UInt(INPUT, p(XLen))
val interrupts = new TileInterrupts().asInput
@ -49,7 +63,7 @@ class RocketTile(implicit p: Parameters) extends LazyModule {
val nRocc = buildRocc.size
val nFPUPorts = buildRocc.filter(_.useFPU).size
val core = Module(new Rocket)
val core = Module(new Rocket()(dcacheParams))
val icache = Module(new Frontend()(icacheParams))
val ptwPorts = ListBuffer(icache.io.ptw, dcache.module.io.ptw)
@ -108,7 +122,7 @@ class RocketTile(implicit p: Parameters) extends LazyModule {
uncachedArbPorts ++= roccs.flatMap(_.io.utl) // TODO no difference between io.autl and io.utl for now
}
val uncachedArb = Module(new ClientUncachedTileLinkIOArbiter(uncachedArbPorts.size))
val uncachedArb = Module(new ClientUncachedTileLinkIOArbiter(uncachedArbPorts.size)(icacheParams))
uncachedArb.io.in <> uncachedArbPorts
ucLegacy.module.io.legacy <> uncachedArb.io.out

2
src/main/scala/uncore/axi4/Parameters.scala
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@ -8,7 +8,7 @@ import scala.math.max
case class AXI4SlaveParameters(
address: Seq[AddressSet],
regionType: RegionType.T = RegionType.GET_EFFECTS,
regionType: RegionType.T = RegionType.UNCACHED,
executable: Boolean = false, // processor can execute from this memory
nodePath: Seq[BaseNode] = Seq(),
supportsWrite: TransferSizes = TransferSizes.none,