periphery: peripheryBusBytes and socBusBytes
This commit is contained in:
parent
35877e6ec1
commit
62f5727bc6
@ -38,7 +38,9 @@ case object ZeroConfig extends Field[ZeroConfig]
|
||||
trait HasPeripheryParameters {
|
||||
implicit val p: Parameters
|
||||
def peripheryBusConfig = p(PeripheryBusConfig)
|
||||
def peripheryBusBytes = peripheryBusConfig.beatBytes
|
||||
def socBusConfig = p(SOCBusConfig)
|
||||
def socBusBytes = socBusConfig.beatBytes
|
||||
def cacheBlockBytes = p(CacheBlockBytes)
|
||||
def peripheryBusArithmetic = p(PeripheryBusArithmetic)
|
||||
def nMemoryChannels = p(coreplex.BankedL2Config).nMemoryChannels
|
||||
|
Loading…
Reference in New Issue
Block a user