riscv/rocket-chip
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[rocketchip] BigInt cast

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This commit is contained in:
Henry Cook 2016-11-16 18:11:06 -08:00
parent da7ecfd189
commit 84f249bd03
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocketchip/Periphery.scala
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@ -174,7 +174,7 @@ trait PeripheryMasterAXI4MMIO {
val mmio_axi4 = AXI4BlindOutputNode(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(p(ExtBusBase), p(ExtBusSize)-1)),
address = List(AddressSet(BigInt(p(ExtBusBase)), p(ExtBusSize)-1)),
executable = true, // Can we run programs on this memory?
supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
supportsRead = TransferSizes(1, 256),