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Merge pull request #562 from ucb-bar/periphery-adjustments

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Periphery adjustments
This commit is contained in:
Henry Cook
2017-03-02 11:14:07 -08:00
committed by GitHub
parent 859416de73 9544b8007e
commit 3a55a1afae
18 changed files with 138 additions and 121 deletions
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2
chisel3

Submodule chisel3 updated: cae110e06d...3e6ef13ff5

2
firrtl

Submodule firrtl updated: 8528ba7680...7f280a5b08

21
src/main/scala/diplomacy/Nodes.scala
View File

@@ -4,6 +4,7 @@ package diplomacy
import Chisel._
import config._
import util.HeterogeneousBag
import scala.collection.mutable.ListBuffer
import chisel3.internal.sourceinfo.SourceInfo
@@ -14,7 +15,7 @@ import chisel3.internal.sourceinfo.SourceInfo
trait InwardNodeImp[DI, UI, EI, BI <: Data]
{
def edgeI(pd: DI, pu: UI): EI
def bundleI(ei: Seq[EI]): Vec[BI]
def bundleI(ei: EI): BI
def colour: String
def connect(bindings: () => Seq[(EI, BI, BI)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
(None, () => bindings().foreach { case (_, i, o) => i <> o })
@@ -33,7 +34,7 @@ trait InwardNodeImp[DI, UI, EI, BI <: Data]
trait OutwardNodeImp[DO, UO, EO, BO <: Data]
{
def edgeO(pd: DO, pu: UO): EO
def bundleO(eo: Seq[EO]): Vec[BO]
def bundleO(eo: EO): BO
// optional methods to track node graph
def mixO(pd: DO, node: OutwardNode[DO, UO, BO]): DO = pd // insert node into parameters
@@ -112,7 +113,7 @@ trait InwardNode[DI, UI, BI <: Data] extends BaseNode with InwardNodeHandle[DI,
protected[diplomacy] val iStar: Int
protected[diplomacy] val iPortMapping: Seq[(Int, Int)]
protected[diplomacy] val iParams: Seq[UI]
val bundleIn: Vec[BI]
val bundleIn: HeterogeneousBag[BI]
}
trait OutwardNodeHandle[DO, UO, BO <: Data]
@@ -145,7 +146,7 @@ trait OutwardNode[DO, UO, BO <: Data] extends BaseNode with OutwardNodeHandle[DO
protected[diplomacy] val oStar: Int
protected[diplomacy] val oPortMapping: Seq[(Int, Int)]
protected[diplomacy] val oParams: Seq[DO]
val bundleOut: Vec[BO]
val bundleOut: HeterogeneousBag[BO]
}
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
@@ -218,14 +219,14 @@ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
lazy val externalEdgesIn = if (externalIn) {edgesIn} else { Seq() }
val flip = false // needed for blind nodes
private def flipO(b: Vec[BO]) = if (flip) b.flip else b
private def flipI(b: Vec[BI]) = if (flip) b else b.flip
private def flipO(b: HeterogeneousBag[BO]) = if (flip) b.flip else b
private def flipI(b: HeterogeneousBag[BI]) = if (flip) b else b.flip
val wire = false // needed if you want to grab access to from inside a module
private def wireO(b: Vec[BO]) = if (wire) Wire(b) else b
private def wireI(b: Vec[BI]) = if (wire) Wire(b) else b
private def wireO(b: HeterogeneousBag[BO]) = if (wire) Wire(b) else b
private def wireI(b: HeterogeneousBag[BI]) = if (wire) Wire(b) else b
lazy val bundleOut = wireO(flipO(outer.bundleO(edgesOut)))
lazy val bundleIn = wireI(flipI(inner.bundleI(edgesIn)))
lazy val bundleOut = wireO(flipO(HeterogeneousBag(edgesOut.map(outer.bundleO(_)))))
lazy val bundleIn = wireI(flipI(HeterogeneousBag(edgesIn .map(inner.bundleI(_)))))
// connects the outward part of a node with the inward part of this node
private def bind(h: OutwardNodeHandle[DI, UI, BI], binding: NodeBinding)(implicit p: Parameters, sourceInfo: SourceInfo): Option[LazyModule] = {

40
src/main/scala/rocketchip/BaseTop.scala
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@@ -12,6 +12,7 @@ import uncore.devices._
import util._
import rocket._
/** BareTop is the root class for creating a top-level RTL module */
abstract class BareTop(implicit p: Parameters) extends LazyModule {
ElaborationArtefacts.add("graphml", graphML)
}
@@ -26,17 +27,20 @@ abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _
val io = _io ()
}
/** Base Top with no Periphery */
trait TopNetwork extends HasPeripheryParameters {
val module: TopNetworkModule
/** HasTopLevelNetworks provides buses that will serve as attachment points,
* for use in sub-traits that connect individual agents or external ports.
*/
trait HasTopLevelNetworks extends HasPeripheryParameters {
val module: HasTopLevelNetworksModule
// Add a SoC and peripheral bus
val socBus = LazyModule(new TLXbar)
val peripheryBus = LazyModule(new TLXbar)
val intBus = LazyModule(new IntXbar)
val l2 = LazyModule(new TLBuffer)
val mem = Seq.fill(p(coreplex.BankedL2Config).nMemoryChannels) { LazyModule(new TLXbar) }
val socBus = LazyModule(new TLXbar) // Wide or unordered-access slave devices (TL-UH)
val peripheryBus = LazyModule(new TLXbar) // Narrow and ordered-access slave devices (TL-UL)
val intBus = LazyModule(new IntXbar) // Interrupts
val l2FrontendBus = LazyModule(new TLBuffer) // Master devices talking to the frontside of the L2
val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM
// The peripheryBus hangs off of socBus;
// here we convert TL-UH -> TL-UL
peripheryBus.node :=
TLBuffer()(
TLWidthWidget(socBusConfig.beatBytes)(
@@ -44,23 +48,23 @@ trait TopNetwork extends HasPeripheryParameters {
socBus.node)))
}
trait TopNetworkBundle extends HasPeripheryParameters {
val outer: TopNetwork
trait HasTopLevelNetworksBundle extends HasPeripheryParameters {
val outer: HasTopLevelNetworks
}
trait TopNetworkModule extends HasPeripheryParameters {
val io: TopNetworkBundle
val outer: TopNetwork
trait HasTopLevelNetworksModule extends HasPeripheryParameters {
val outer: HasTopLevelNetworks
val io: HasTopLevelNetworksBundle
}
/** Base Top with no Periphery */
/** Base Top class with no peripheral devices or ports added */
class BaseTop(implicit p: Parameters) extends BareTop
with TopNetwork {
with HasTopLevelNetworks {
override lazy val module = new BaseTopModule(this, () => new BaseTopBundle(this))
}
class BaseTopBundle[+L <: BaseTop](_outer: L) extends BareTopBundle(_outer)
with TopNetworkBundle
with HasTopLevelNetworksBundle
class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io)
with TopNetworkModule
with HasTopLevelNetworksModule

93
src/main/scala/rocketchip/Periphery.scala
View File

@@ -37,18 +37,22 @@ case object ZeroConfig extends Field[ZeroConfig]
/** Utility trait for quick access to some relevant parameters */
trait HasPeripheryParameters {
implicit val p: Parameters
lazy val peripheryBusConfig = p(PeripheryBusConfig)
lazy val socBusConfig = p(SOCBusConfig)
lazy val cacheBlockBytes = p(CacheBlockBytes)
lazy val peripheryBusArithmetic = p(PeripheryBusArithmetic)
def peripheryBusConfig = p(PeripheryBusConfig)
def peripheryBusBytes = peripheryBusConfig.beatBytes
def socBusConfig = p(SOCBusConfig)
def socBusBytes = socBusConfig.beatBytes
def cacheBlockBytes = p(CacheBlockBytes)
def peripheryBusArithmetic = p(PeripheryBusArithmetic)
def nMemoryChannels = p(coreplex.BankedL2Config).nMemoryChannels
}
/////
trait PeripheryExtInterrupts {
this: TopNetwork =>
this: HasTopLevelNetworks =>
val extInterrupts = IntBlindInputNode(p(NExtTopInterrupts))
val nExtInterrupts = p(NExtTopInterrupts)
val extInterrupts = IntInternalInputNode(nExtInterrupts)
val extInterruptXing = LazyModule(new IntXing)
intBus.intnode := extInterruptXing.intnode
@@ -56,23 +60,24 @@ trait PeripheryExtInterrupts {
}
trait PeripheryExtInterruptsBundle {
this: TopNetworkBundle {
this: HasTopLevelNetworksBundle {
val outer: PeripheryExtInterrupts
} =>
val interrupts = outer.extInterrupts.bundleIn
val interrupts = UInt(INPUT, width = outer.nExtInterrupts)
}
trait PeripheryExtInterruptsModule {
this: TopNetworkModule {
this: HasTopLevelNetworksModule {
val outer: PeripheryExtInterrupts
val io: PeripheryExtInterruptsBundle
} =>
outer.extInterrupts.bundleIn(0).zipWithIndex.foreach { case(o, i) => o := io.interrupts(i) }
}
/////
trait PeripheryMasterAXI4Mem {
this: TopNetwork =>
this: HasTopLevelNetworks =>
val module: PeripheryMasterAXI4MemModule
private val config = p(ExtMem)
@@ -105,14 +110,14 @@ trait PeripheryMasterAXI4Mem {
}
trait PeripheryMasterAXI4MemBundle {
this: TopNetworkBundle {
this: HasTopLevelNetworksBundle {
val outer: PeripheryMasterAXI4Mem
} =>
val mem_axi4 = outer.mem_axi4.bundleOut
}
trait PeripheryMasterAXI4MemModule {
this: TopNetworkModule {
this: HasTopLevelNetworksModule {
val outer: PeripheryMasterAXI4Mem
val io: PeripheryMasterAXI4MemBundle
} =>
@@ -121,7 +126,7 @@ trait PeripheryMasterAXI4MemModule {
/////
trait PeripheryZero {
this: TopNetwork =>
this: HasTopLevelNetworks =>
val module: PeripheryZeroModule
private val config = p(ZeroConfig)
@@ -136,13 +141,13 @@ trait PeripheryZero {
}
trait PeripheryZeroBundle {
this: TopNetworkBundle {
this: HasTopLevelNetworksBundle {
val outer: PeripheryZero
} =>
}
trait PeripheryZeroModule {
this: TopNetworkModule {
this: HasTopLevelNetworksModule {
val outer: PeripheryZero
val io: PeripheryZeroBundle
} =>
@@ -152,7 +157,7 @@ trait PeripheryZeroModule {
// PeripheryMasterAXI4MMIO is an example, make your own cake pattern like this one.
trait PeripheryMasterAXI4MMIO {
this: TopNetwork =>
this: HasTopLevelNetworks =>
private val config = p(ExtBus)
val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters(
@@ -173,14 +178,14 @@ trait PeripheryMasterAXI4MMIO {
}
trait PeripheryMasterAXI4MMIOBundle {
this: TopNetworkBundle {
this: HasTopLevelNetworksBundle {
val outer: PeripheryMasterAXI4MMIO
} =>
val mmio_axi4 = outer.mmio_axi4.bundleOut
}
trait PeripheryMasterAXI4MMIOModule {
this: TopNetworkModule {
this: HasTopLevelNetworksModule {
val outer: PeripheryMasterAXI4MMIO
val io: PeripheryMasterAXI4MMIOBundle
} =>
@@ -190,26 +195,26 @@ trait PeripheryMasterAXI4MMIOModule {
/////
// PeripherySlaveAXI4 is an example, make your own cake pattern like this one.
trait PeripherySlaveAXI4 extends TopNetwork {
trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
private val config = p(ExtIn)
val l2_axi4 = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
val l2FrontendAXI4Node = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
masters = Seq(AXI4MasterParameters(
id = IdRange(0, 1 << config.idBits))))))
l2.node :=
l2FrontendBus.node :=
TLSourceShrinker(1 << config.sourceBits)(
TLWidthWidget(config.beatBytes)(
AXI4ToTL()(
AXI4Fragmenter()(
l2_axi4))))
l2FrontendAXI4Node))))
}
trait PeripherySlaveAXI4Bundle extends TopNetworkBundle {
trait PeripherySlaveAXI4Bundle extends HasTopLevelNetworksBundle {
val outer: PeripherySlaveAXI4
val l2_axi4 = outer.l2_axi4.bundleIn
val l2_frontend_bus_axi4 = outer.l2FrontendAXI4Node.bundleIn
}
trait PeripherySlaveAXI4Module extends TopNetworkModule {
trait PeripherySlaveAXI4Module extends HasTopLevelNetworksModule {
val outer: PeripherySlaveAXI4
val io: PeripherySlaveAXI4Bundle
// nothing to do
@@ -219,7 +224,7 @@ trait PeripherySlaveAXI4Module extends TopNetworkModule {
// Add an external TL-UL slave
trait PeripheryMasterTLMMIO {
this: TopNetwork =>
this: HasTopLevelNetworks =>
private val config = p(ExtBus)
val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters(
@@ -239,14 +244,14 @@ trait PeripheryMasterTLMMIO {
}
trait PeripheryMasterTLMMIOBundle {
this: TopNetworkBundle {
this: HasTopLevelNetworksBundle {
val outer: PeripheryMasterTLMMIO
} =>
val mmio_tl = outer.mmio_tl.bundleOut
}
trait PeripheryMasterTLMMIOModule {
this: TopNetworkModule {
this: HasTopLevelNetworksModule {
val outer: PeripheryMasterTLMMIO
val io: PeripheryMasterTLMMIOBundle
} =>
@@ -256,24 +261,24 @@ trait PeripheryMasterTLMMIOModule {
/////
// NOTE: this port is NOT allowed to issue Acquires
trait PeripherySlaveTL extends TopNetwork {
trait PeripherySlaveTL extends HasTopLevelNetworks {
private val config = p(ExtIn)
val l2_tl = TLBlindInputNode(Seq(TLClientPortParameters(
val l2FrontendTLNode = TLBlindInputNode(Seq(TLClientPortParameters(
clients = Seq(TLClientParameters(
sourceId = IdRange(0, 1 << config.idBits))))))
l2.node :=
l2FrontendBus.node :=
TLSourceShrinker(1 << config.sourceBits)(
TLWidthWidget(config.beatBytes)(
l2_tl))
l2FrontendTLNode))
}
trait PeripherySlaveTLBundle extends TopNetworkBundle {
trait PeripherySlaveTLBundle extends HasTopLevelNetworksBundle {
val outer: PeripherySlaveTL
val l2_tl = outer.l2_tl.bundleIn
val l2_frontend_bus_tl = outer.l2FrontendTLNode.bundleIn
}
trait PeripherySlaveTLModule extends TopNetworkModule {
trait PeripherySlaveTLModule extends HasTopLevelNetworksModule {
val outer: PeripherySlaveTL
val io: PeripherySlaveTLBundle
// nothing to do
@@ -282,7 +287,7 @@ trait PeripherySlaveTLModule extends TopNetworkModule {
/////
trait PeripheryBootROM {
this: TopNetwork =>
this: HasTopLevelNetworks =>
val coreplex: CoreplexRISCVPlatform
private val bootrom_address = 0x1000
@@ -293,13 +298,13 @@ trait PeripheryBootROM {
}
trait PeripheryBootROMBundle {
this: TopNetworkBundle {
this: HasTopLevelNetworksBundle {
val outer: PeripheryBootROM
} =>
}
trait PeripheryBootROMModule {
this: TopNetworkModule {
this: HasTopLevelNetworksModule {
val outer: PeripheryBootROM
val io: PeripheryBootROMBundle
} =>
@@ -308,20 +313,20 @@ trait PeripheryBootROMModule {
/////
trait PeripheryTestRAM {
this: TopNetwork =>
this: HasTopLevelNetworks =>
val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, peripheryBusConfig.beatBytes))
testram.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
}
trait PeripheryTestRAMBundle {
this: TopNetworkBundle {
this: HasTopLevelNetworksBundle {
val outer: PeripheryTestRAM
} =>
}
trait PeripheryTestRAMModule {
this: TopNetworkModule {
this: HasTopLevelNetworksModule {
val outer: PeripheryTestRAM
val io: PeripheryTestRAMBundle
} =>
@@ -330,19 +335,19 @@ trait PeripheryTestRAMModule {
/////
trait PeripheryTestBusMaster {
this: TopNetwork =>
this: HasTopLevelNetworks =>
val fuzzer = LazyModule(new TLFuzzer(5000))
peripheryBus.node := fuzzer.node
}
trait PeripheryTestBusMasterBundle {
this: TopNetworkBundle {
this: HasTopLevelNetworksBundle {
val outer: PeripheryTestBusMaster
} =>
}
trait PeripheryTestBusMasterModule {
this: TopNetworkModule {
this: HasTopLevelNetworksModule {
val outer: PeripheryTestBusMaster
val io: PeripheryTestBusMasterBundle
} =>

30
src/main/scala/rocketchip/RISCVPlatform.scala
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@@ -13,18 +13,18 @@ import coreplex._
/// Core with JTAG for debug only
trait PeripheryJTAG extends TopNetwork {
trait PeripheryJTAG extends HasTopLevelNetworks {
val module: PeripheryJTAGModule
val coreplex: CoreplexRISCVPlatform
}
trait PeripheryJTAGBundle extends TopNetworkBundle {
trait PeripheryJTAGBundle extends HasTopLevelNetworksBundle {
val outer: PeripheryJTAG
val jtag = new JTAGIO(true).flip
}
trait PeripheryJTAGModule extends TopNetworkModule {
trait PeripheryJTAGModule extends HasTopLevelNetworksModule {
val outer: PeripheryJTAG
val io: PeripheryJTAGBundle
@@ -38,18 +38,18 @@ trait PeripheryJTAGModule extends TopNetworkModule {
/// Core with DTM for debug only
trait PeripheryDTM extends TopNetwork {
trait PeripheryDTM extends HasTopLevelNetworks {
val module: PeripheryDTMModule
val coreplex: CoreplexRISCVPlatform
}
trait PeripheryDTMBundle extends TopNetworkBundle {
trait PeripheryDTMBundle extends HasTopLevelNetworksBundle {
val outer: PeripheryDTM
val debug = new DebugBusIO().flip
}
trait PeripheryDTMModule extends TopNetworkModule {
trait PeripheryDTMModule extends HasTopLevelNetworksModule {
val outer: PeripheryDTM
val io: PeripheryDTMBundle
@@ -58,19 +58,19 @@ trait PeripheryDTMModule extends TopNetworkModule {
/// Core with DTM or JTAG based on a parameter
trait PeripheryDebug extends TopNetwork {
trait PeripheryDebug extends HasTopLevelNetworks {
val module: PeripheryDebugModule
val coreplex: CoreplexRISCVPlatform
}
trait PeripheryDebugBundle extends TopNetworkBundle {
trait PeripheryDebugBundle extends HasTopLevelNetworksBundle {
val outer: PeripheryDebug
val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO().flip)
val jtag = (p(IncludeJtagDTM)).option(new JTAGIO(true).flip)
}
trait PeripheryDebugModule extends TopNetworkModule {
trait PeripheryDebugModule extends HasTopLevelNetworksModule {
val outer: PeripheryDebug
val io: PeripheryDebugBundle
@@ -86,16 +86,16 @@ trait PeripheryDebugModule extends TopNetworkModule {
/// Real-time clock is based on RTCPeriod relative to Top clock
trait PeripheryCounter extends TopNetwork {
trait PeripheryCounter extends HasTopLevelNetworks {
val module: PeripheryCounterModule
val coreplex: CoreplexRISCVPlatform
}
trait PeripheryCounterBundle extends TopNetworkBundle {
trait PeripheryCounterBundle extends HasTopLevelNetworksBundle {
val outer: PeripheryCounter
}
trait PeripheryCounterModule extends TopNetworkModule {
trait PeripheryCounterModule extends HasTopLevelNetworksModule {
val outer: PeripheryCounter
val io: PeripheryCounterBundle
@@ -111,16 +111,16 @@ trait PeripheryCounterModule extends TopNetworkModule {
/// Coreplex will power-on running at 0x1000 (BootROM)
trait HardwiredResetVector extends TopNetwork {
trait HardwiredResetVector extends HasTopLevelNetworks {
val module: HardwiredResetVectorModule
val coreplex: CoreplexRISCVPlatform
}
trait HardwiredResetVectorBundle extends TopNetworkBundle {
trait HardwiredResetVectorBundle extends HasTopLevelNetworksBundle {
val outer: HardwiredResetVector
}
trait HardwiredResetVectorModule extends TopNetworkModule {
trait HardwiredResetVectorModule extends HasTopLevelNetworksModule {
val outer: HardwiredResetVector
val io: HardwiredResetVectorBundle

8
src/main/scala/rocketchip/RocketPlexMaster.scala
View File

@@ -10,12 +10,12 @@ import uncore.devices._
import util._
import coreplex._
trait RocketPlexMaster extends TopNetwork {
trait RocketPlexMaster extends HasTopLevelNetworks {
val module: RocketPlexMasterModule
val coreplex = LazyModule(new DefaultCoreplex)
coreplex.l2in :=* l2.node
coreplex.l2in :=* l2FrontendBus.node
socBus.node := coreplex.mmio
coreplex.mmioInt := intBus.intnode
@@ -23,11 +23,11 @@ trait RocketPlexMaster extends TopNetwork {
(mem zip coreplex.mem) foreach { case (xbar, channel) => xbar.node :=* channel }
}
trait RocketPlexMasterBundle extends TopNetworkBundle {
trait RocketPlexMasterBundle extends HasTopLevelNetworksBundle {
val outer: RocketPlexMaster
}
trait RocketPlexMasterModule extends TopNetworkModule {
trait RocketPlexMasterModule extends HasTopLevelNetworksModule {
val outer: RocketPlexMaster
val io: RocketPlexMasterBundle
val clock: Clock

5
src/main/scala/rocketchip/TestHarness.scala
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@@ -15,8 +15,7 @@ class TestHarness()(implicit p: Parameters) extends Module {
}
val dut = Module(LazyModule(new ExampleRocketTop).module)
for (int <- dut.io.interrupts(0))
int := Bool(false)
dut.io.interrupts := UInt(0)
val channels = p(coreplex.BankedL2Config).nMemoryChannels
if (channels > 0) Module(LazyModule(new SimAXIMem(channels)).module).io.axi4 <> dut.io.mem_axi4
@@ -30,7 +29,7 @@ class TestHarness()(implicit p: Parameters) extends Module {
val mmio_sim = Module(LazyModule(new SimAXIMem(1, 4096)).module)
mmio_sim.io.axi4 <> dut.io.mmio_axi4
val l2_axi4 = dut.io.l2_axi4(0)
val l2_axi4 = dut.io.l2_frontend_bus_axi4(0)
l2_axi4.ar.valid := Bool(false)
l2_axi4.aw.valid := Bool(false)
l2_axi4.w .valid := Bool(false)

4
src/main/scala/uncore/ahb/Nodes.scala
View File

@@ -12,8 +12,8 @@ object AHBImp extends NodeImp[AHBMasterPortParameters, AHBSlavePortParameters, A
def edgeO(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu)
def edgeI(pd: AHBMasterPortParameters, pu: AHBSlavePortParameters): AHBEdgeParameters = AHBEdgeParameters(pd, pu)
def bundleO(eo: Seq[AHBEdgeParameters]): Vec[AHBBundle] = Vec(eo.size, AHBBundle(AHBBundleParameters.union(eo.map(_.bundle))))
def bundleI(ei: Seq[AHBEdgeParameters]): Vec[AHBBundle] = Vec(ei.size, AHBBundle(AHBBundleParameters.union(ei.map(_.bundle))))
def bundleO(eo: AHBEdgeParameters): AHBBundle = AHBBundle(eo.bundle)
def bundleI(ei: AHBEdgeParameters): AHBBundle = AHBBundle(ei.bundle)
def colour = "#00ccff" // bluish
override def labelI(ei: AHBEdgeParameters) = (ei.slave.beatBytes * 8).toString

2
src/main/scala/uncore/ahb/RegisterRouter.scala
View File

@@ -80,7 +80,7 @@ abstract class AHBRegisterRouterBase(address: AddressSet, interrupts: Int, concu
val intnode = uncore.tilelink2.IntSourceNode(interrupts)
}
case class AHBRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AHBBundle])(implicit val p: Parameters)
case class AHBRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AHBBundle])(implicit val p: Parameters)
class AHBRegBundleBase(arg: AHBRegBundleArg) extends Bundle
{

4
src/main/scala/uncore/apb/Nodes.scala
View File

@@ -12,8 +12,8 @@ object APBImp extends NodeImp[APBMasterPortParameters, APBSlavePortParameters, A
def edgeO(pd: APBMasterPortParameters, pu: APBSlavePortParameters): APBEdgeParameters = APBEdgeParameters(pd, pu)
def edgeI(pd: APBMasterPortParameters, pu: APBSlavePortParameters): APBEdgeParameters = APBEdgeParameters(pd, pu)
def bundleO(eo: Seq[APBEdgeParameters]): Vec[APBBundle] = Vec(eo.size, APBBundle(APBBundleParameters.union(eo.map(_.bundle))))
def bundleI(ei: Seq[APBEdgeParameters]): Vec[APBBundle] = Vec(ei.size, APBBundle(APBBundleParameters.union(ei.map(_.bundle))))
def bundleO(eo: APBEdgeParameters): APBBundle = APBBundle(eo.bundle)
def bundleI(ei: APBEdgeParameters): APBBundle = APBBundle(ei.bundle)
def colour = "#00ccff" // bluish
override def labelI(ei: APBEdgeParameters) = (ei.slave.beatBytes * 8).toString

2
src/main/scala/uncore/apb/RegisterRouter.scala
View File

@@ -64,7 +64,7 @@ abstract class APBRegisterRouterBase(address: AddressSet, interrupts: Int, concu
val intnode = uncore.tilelink2.IntSourceNode(interrupts)
}
case class APBRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[APBBundle])(implicit val p: Parameters)
case class APBRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[APBBundle])(implicit val p: Parameters)
class APBRegBundleBase(arg: APBRegBundleArg) extends Bundle
{

4
src/main/scala/uncore/axi4/Nodes.scala
View File

@@ -12,8 +12,8 @@ object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters
def edgeO(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu)
def edgeI(pd: AXI4MasterPortParameters, pu: AXI4SlavePortParameters): AXI4EdgeParameters = AXI4EdgeParameters(pd, pu)
def bundleO(eo: Seq[AXI4EdgeParameters]): Vec[AXI4Bundle] = Vec(eo.size, AXI4Bundle(AXI4BundleParameters.union(eo.map(_.bundle))))
def bundleI(ei: Seq[AXI4EdgeParameters]): Vec[AXI4Bundle] = Vec(ei.size, AXI4Bundle(AXI4BundleParameters.union(ei.map(_.bundle))))
def bundleO(eo: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(eo.bundle)
def bundleI(ei: AXI4EdgeParameters): AXI4Bundle = AXI4Bundle(ei.bundle)
def colour = "#00ccff" // bluish
override def labelI(ei: AXI4EdgeParameters) = (ei.slave.beatBytes * 8).toString

2
src/main/scala/uncore/axi4/RegisterRouter.scala
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@@ -85,7 +85,7 @@ abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, conc
val intnode = uncore.tilelink2.IntSourceNode(interrupts)
}
case class AXI4RegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AXI4Bundle])(implicit val p: Parameters)
case class AXI4RegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[AXI4Bundle])(implicit val p: Parameters)
class AXI4RegBundleBase(arg: AXI4RegBundleArg) extends Bundle
{

14
src/main/scala/uncore/tilelink2/IntNodes.scala
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@@ -53,14 +53,8 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In
{
def edgeO(pd: IntSourcePortParameters, pu: IntSinkPortParameters): IntEdge = IntEdge(pd, pu)
def edgeI(pd: IntSourcePortParameters, pu: IntSinkPortParameters): IntEdge = IntEdge(pd, pu)
def bundleO(eo: Seq[IntEdge]): Vec[Vec[Bool]] = {
if (eo.isEmpty) Vec(0, Vec(0, Bool())) else
Vec(eo.size, Vec(eo.map(_.source.num).max, Bool()))
}
def bundleI(ei: Seq[IntEdge]): Vec[Vec[Bool]] = {
if (ei.isEmpty) Vec(0, Vec(0, Bool())) else
Vec(ei.size, Vec(ei.map(_.source.num).max, Bool()))
}
def bundleO(eo: IntEdge): Vec[Bool] = Vec(eo.source.num, Bool())
def bundleI(ei: IntEdge): Vec[Bool] = Vec(ei.source.num, Bool())
def colour = "#0000ff" // blue
override def labelI(ei: IntEdge) = ei.source.sources.map(_.range.size).sum.toString
@@ -132,6 +126,8 @@ class IntXing()(implicit p: Parameters) extends LazyModule
val out = intnode.bundleOut
}
io.out := RegNext(RegNext(RegNext(io.in)))
(io.in zip io.out) foreach { case (in, out) =>
out := RegNext(RegNext(RegNext(in)))
}
}
}

12
src/main/scala/uncore/tilelink2/Nodes.scala
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@@ -18,8 +18,8 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(pd, pu)
def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeIn = new TLEdgeIn(pd, pu)
def bundleO(eo: Seq[TLEdgeOut]): Vec[TLBundle] = Vec(eo.size, TLBundle(TLBundleParameters.union(eo.map(_.bundle))))
def bundleI(ei: Seq[TLEdgeIn]): Vec[TLBundle] = Vec(ei.size, TLBundle(TLBundleParameters.union(ei.map(_.bundle))))
def bundleO(eo: TLEdgeOut): TLBundle = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn): TLBundle = TLBundle(ei.bundle)
def colour = "#000000" // black
override def labelI(ei: TLEdgeIn) = (ei.manager.beatBytes * 8).toString
@@ -156,8 +156,8 @@ object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPor
def edgeO(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu)
def edgeI(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters): TLAsyncEdgeParameters = TLAsyncEdgeParameters(pd, pu)
def bundleO(eo: Seq[TLAsyncEdgeParameters]): Vec[TLAsyncBundle] = Vec(eo.size, new TLAsyncBundle(TLAsyncBundleParameters.union(eo.map(_.bundle))))
def bundleI(ei: Seq[TLAsyncEdgeParameters]): Vec[TLAsyncBundle] = Vec(ei.size, new TLAsyncBundle(TLAsyncBundleParameters.union(ei.map(_.bundle))))
def bundleO(eo: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(eo.bundle)
def bundleI(ei: TLAsyncEdgeParameters): TLAsyncBundle = new TLAsyncBundle(ei.bundle)
def colour = "#ff0000" // red
override def labelI(ei: TLAsyncEdgeParameters) = ei.manager.depth.toString
@@ -188,8 +188,8 @@ object TLRationalImp extends NodeImp[TLRationalClientPortParameters, TLRationalM
def edgeO(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu)
def edgeI(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters): TLRationalEdgeParameters = TLRationalEdgeParameters(pd, pu)
def bundleO(eo: Seq[TLRationalEdgeParameters]): Vec[TLRationalBundle] = Vec(eo.size, new TLRationalBundle(TLBundleParameters.union(eo.map(_.bundle))))
def bundleI(ei: Seq[TLRationalEdgeParameters]): Vec[TLRationalBundle] = Vec(ei.size, new TLRationalBundle(TLBundleParameters.union(ei.map(_.bundle))))
def bundleO(eo: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(eo.bundle)
def bundleI(ei: TLRationalEdgeParameters): TLRationalBundle = new TLRationalBundle(ei.bundle)
def colour = "#00ff00" // green

2
src/main/scala/uncore/tilelink2/RegisterRouter.scala
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@@ -86,7 +86,7 @@ abstract class TLRegisterRouterBase(val address: AddressSet, interrupts: Int, co
val intnode = IntSourceNode(interrupts)
}
case class TLRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[TLBundle])(implicit val p: Parameters)
case class TLRegBundleArg(interrupts: util.HeterogeneousBag[Vec[Bool]], in: util.HeterogeneousBag[TLBundle])(implicit val p: Parameters)
class TLRegBundleBase(arg: TLRegBundleArg) extends Bundle
{

12
src/main/scala/util/Misc.scala
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@@ -160,3 +160,15 @@ object Random
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < UInt(round((i << value.getWidth).toDouble / slices)))
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.toBools.toSet)
}