riscv/rocket-chip
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Merge branch 'master' into priv-1.10

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This commit is contained in:
Henry Cook
2017-03-13 11:59:18 -07:00
committed by GitHub
parent dbc8f4b30b 1c6dde8c15
commit 1a3fec61c0
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/uncore/tilelink2/ToAHB.scala
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@@ -30,7 +30,7 @@ case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)(
TLManagerPortParameters(managers, beatBytes, 1, 1)
})
class TLToAHB(combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
class TLToAHB(val combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
{
val node = TLToAHBNode()

2
src/main/scala/uncore/tilelink2/ToAXI4.scala
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@@ -35,7 +35,7 @@ case class TLToAXI4Node(idBits: Int) extends MixedAdapterNode(TLImp, AXI4Imp)(
minLatency = p.minLatency)
})
class TLToAXI4(idBits: Int, combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
class TLToAXI4(val idBits: Int, val combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
{
val node = TLToAXI4Node(idBits)