Andrew Waterman
52d6b0b1a5
Improve ALU QoR
...
Rejigger muxes; share XOR gates between ADD/SUB, XOR, and BEQ.
2016-01-20 17:42:31 -08:00
Howard Mao
e80340198a
use implicit parameters for ALU
2015-11-30 17:35:33 -08:00
Andrew Waterman
e203b8b378
Make ALU generic for zscale
2015-11-24 19:17:07 -08:00
Henry Cook
4f8468b60f
depend on external cde library
2015-10-21 18:19:23 -07:00
Henry Cook
84576650b5
Removed all traces of params
2015-10-05 21:48:05 -07:00
Andrew Waterman
049fc8dc24
Chisel3 compatibility: use BitPat for don't-cares
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This one's hella ugly, but for the time being, idgaf.
2015-07-28 02:48:49 -07:00
Andrew Waterman
f2dcc40e67
Chisel3 compatibility changes
2015-07-27 12:42:20 -07:00
Henry Cook
741e6b77ad
Rename some params, use refactored TileLink
2015-02-01 20:37:31 -08:00
Yunsup Lee
8abf62fae3
add LICENSE
2014-09-12 18:06:41 -07:00
Henry Cook
0dac9a7467
Full conversion to params. Compiles but does not elaborate.
2014-08-19 11:38:02 -07:00
Andrew Waterman
f235fa0db6
Move branch resolution to M stage
2014-04-07 15:58:49 -07:00
Andrew Waterman
243c4ae342
sync up rocket with new isa
2013-09-12 03:44:38 -07:00
Henry Cook
1a9e43aa11
initial attempt at upgrade
2013-08-12 10:39:11 -07:00
Henry Cook
9abdf4e154
Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
2013-07-23 20:27:58 -07:00
Andrew Waterman
05f19b21d0
merge multiplier and divider
2012-12-12 02:22:47 -08:00
Andrew Waterman
c921fc34a9
merge ALU left and right shifters
2012-12-12 02:22:34 -08:00
Andrew Waterman
f5c53ce35d
add ecc support to d$ data rams
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i haven't injected errors yet; it may well be incorrect.
2012-12-11 15:58:53 -08:00
Andrew Waterman
29bc361d6c
remove global constants; disentangle hwacha a bit
2012-11-17 17:24:08 -08:00
Henry Cook
88ac5af181
Merged consts-as-traits
2012-10-16 16:32:35 -07:00
Andrew Waterman
661f8e635b
merge I$, ITLB, BTB into Frontend
2012-10-16 02:24:37 -07:00
Henry Cook
dfdfddebe8
constants as traits
2012-10-07 22:20:03 -07:00
Huy Vo
fd95159837
INPUT/OUTPUT orderring swapped
2012-07-12 18:16:57 -07:00
Andrew Waterman
eafdffe125
simplify page table walker; speed up emulator
2012-05-01 01:24:36 -07:00
Andrew Waterman
cfca2d1411
clean up cache interfaces; avoid reserved keywords
2012-03-16 00:44:16 -07:00
Yunsup Lee
94ba32bbd3
change package name and sbt project name to rocket
2012-02-25 17:09:26 -08:00
Yunsup Lee
a51c7cc927
new build system with updated chisel, hwacha
2012-02-14 19:43:59 -08:00
Andrew Waterman
e9da2cf66a
improve id/ex datapath
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move operand selection into decode stage; simplify bypassing
2012-02-08 06:47:26 -08:00
Henry Cook
1d76255dc1
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 14:39:57 -08:00
Andrew Waterman
eb657dd250
reduce superfluous replays
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we only replay after a cache miss if we mis-scheduled the use of a load.
2012-01-01 21:28:38 -08:00
Andrew Waterman
efc623cc36
validate BTB address and use BTB for J/JAL/JR/JALR
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even if we weren't using the BTB for JR/JALR, we'd need to
flush the BTB on FENCE.I and on context switches, but
validating its result suffices instead.
2012-01-01 17:04:14 -08:00
Andrew Waterman
96c78829b4
improve ALU and fix revealed emulator bug
2011-12-17 07:20:32 -08:00
Rimas Avizienis
9aca403aa8
more itlb integration & cleanup
2011-11-09 23:18:14 -08:00
Rimas Avizienis
c06e2d16e4
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-25 23:02:47 -07:00
