92 lines
3.0 KiB
Scala
92 lines
3.0 KiB
Scala
package Top {
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import Chisel._
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import Node._;
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import Constants._
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import Instructions._
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class ioALU extends Bundle(){
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val dw = UFix(1, 'input);
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val fn = UFix(4, 'input);
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val shamt = UFix(6, 'input);
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val in2 = UFix(64, 'input);
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val in1 = UFix(64, 'input);
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val out = UFix(64, 'output);
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}
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class rocketDpathALU extends Component
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{
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val io = new ioALU();
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val out64 =
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MuxCase(Fix(0, 64), Array(
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(io.fn === FN_ADD) -> (io.in1 + io.in2).toFix,
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(io.fn === FN_SUB) -> (io.in1 - io.in2).toFix,
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(io.fn === FN_SLT) -> (io.in1.toFix < io.in2.toFix), //(io.in1 < io.in2)
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(io.fn === FN_SLTU) -> (io.in1 < io.in2).toFix,
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(io.fn === FN_AND) -> (io.in1 & io.in2).toFix,
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(io.fn === FN_OR) -> (io.in1 | io.in2).toFix,
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(io.fn === FN_XOR) -> (io.in1 ^ io.in2).toFix,
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(io.fn === FN_SL) -> (io.in1 << io.shamt).toFix,
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(io.fn === FN_SR && io.dw === DW_64) -> (io.in1 >> io.shamt).toFix,
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(io.fn === FN_SR && io.dw === DW_32) -> (Cat(Fix(0, 32),io.in1(31, 0)).toUFix >> io.shamt),
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(io.fn === FN_SRA) -> (io.in1.toFix >>> io.shamt)));
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io.out := MuxLookup(io.dw, Fix(0, 64), Array(
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DW_64 -> out64(63,0),
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DW_32 -> Cat(Fill(32, out64(31)), out64(31,0)).toFix)).toUFix;
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}
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/*
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class IoDpathALU extends Bundle {
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val in0 = Bits(32,'input);
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val in1 = Bits(32,'input);
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val fn = Bits(4,'input);
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val out = Bits(32,'output);
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}
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class DpathALU extends Component {
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val io = new IoDpathALU();
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val adder_in0 = MuxCase(io.in0,Array(
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((io.fn === FN_SUB) | (io.fn === FN_SLT) | (io.fn === FN_SLTU)) -> (~io.in0)));
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val adder_in1 = io.in1;
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val adder_cin = MuxCase(Bits(0),Array(
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((io.fn === FN_SUB) | (io.fn === FN_SLT) | (io.fn === FN_SLTU)) -> Bits(1)));
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// Need to make the same width?
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val adder_out = Cat(Bits(0,1),adder_in1).toUFix + Cat(Bits(0,1),adder_in0).toUFix + adder_cin.toUFix;
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//adder_out := (adder_in1.toUFix + adder_in0.toUFix + adder_cin.toUFix);
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// Determine if there is overflow
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val overflow = (io.in0(31) ^ io.in1(31)) & (adder_out(32) != io.in0(31));
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val compare_yes = MuxLookup(io.fn,Bits(0),Array(
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// If unsigned, do subtraction, and if the result is negative, then slt=true
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FN_SLTU -> ~adder_out(32),
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// If signed, do subtraction, and if the result is negative, then slt=true as well
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// But if there is bad overflow (operands same sign and result is a different sign),
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// then need to flip
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FN_SLT -> ~(adder_out(32) ^ overflow)));
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io.out := MuxLookup(io.fn,Fix(0),Array(
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FN_ADD -> adder_out,
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FN_SUB -> adder_out,
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FN_SLT -> compare_yes,
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FN_SLTU -> compare_yes,
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FN_AND -> (io.in0 & io.in1),
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FN_OR -> (io.in0 | io.in1),
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FN_XOR -> (io.in0 ^ io.in1),
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FN_SL -> (io.in1 << io.in0(4,0).toUFix),
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FN_SR -> (io.in1 >> io.in0(4,0).toUFix),
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FN_SRA -> (io.in1.toFix >> io.in0(4,0).toUFix)
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));
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}
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*/
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}
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