Howard Mao
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a44e054c77
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add support for different TileLink and MIF data widths
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2015-10-13 12:46:23 -07:00 |
|
Henry Cook
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9d11b64c75
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added HasAddrMapParameters and GlobalAddrMap
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2015-10-06 18:24:08 -07:00 |
|
Henry Cook
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1c489d75c1
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inject params at top-level for MemDessert
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2015-10-06 16:26:58 -07:00 |
|
Henry Cook
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c4eadbda57
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Removed all traces of params
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2015-10-06 11:42:06 -07:00 |
|
Henry Cook
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38ae2707a3
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refactor MemIO to not use params
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2015-10-06 11:41:48 -07:00 |
|
Henry Cook
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3d10a89907
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refactor NASTI to not use param; new AddrMap class
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2015-10-06 11:41:47 -07:00 |
|
Andrew Waterman
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79cdf6efc0
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Make perf counters optional
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2015-09-28 13:56:08 -07:00 |
|
Howard Mao
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7b0167b92e
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make sure SCR and PCR data width matches xLen
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2015-09-25 12:13:22 -07:00 |
|
Howard Mao
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0d763524ef
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make sure conf address map scales with number of cores
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2015-09-25 09:41:19 -07:00 |
|
Howard Mao
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8d4d8680bf
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replace NASTIMasterIO and NASTISlaveIO with NASTIIO
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2015-09-24 16:59:13 -07:00 |
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Howard Mao
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56ecdff52d
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Implement NASTI-based Mem/IO interconnect
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2015-09-22 10:32:31 -07:00 |
|
Andrew Waterman
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c6bcc832a1
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Chisel3: Don't use Vec.fill for IOs
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2015-09-20 13:43:56 -07:00 |
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Christopher Celio
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c9d89226fb
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Generated *.d file of tests now kept in order
-Changed Set to LinkedHashSet in Testing.scala
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2015-09-11 18:36:04 -07:00 |
|
Andrew Waterman
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700910adff
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Chisel3 compatibility fix for <>
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2015-08-05 15:34:40 -07:00 |
|
Andrew Waterman
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34b9a7fdc5
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Various Chisel3 compatibility changes
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2015-08-03 18:54:56 -07:00 |
|
Henry Cook
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0c9a7817b6
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Reduce outstanding mem accesses for FPGAConfig (to reduce MIFTagBits < 7)
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2015-07-30 16:30:00 -07:00 |
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Henry Cook
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51c42083d0
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Add new junctions repo as submodule (contains externally facing buses and peripherals).
Bump all submodules.
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2015-07-29 18:15:45 -07:00 |
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Henry Cook
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d21ffa4dba
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Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used
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2015-07-28 00:24:07 -07:00 |
|
Yunsup Lee
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efd6458a3d
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add zscale programs
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2015-07-27 19:06:06 -07:00 |
|
Henry Cook
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bd4ff35a4b
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Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS
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2015-07-22 11:49:10 -07:00 |
|
Yunsup Lee
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a99b1e3a01
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append config name to generated Makefrag filename
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2015-07-17 12:34:49 -07:00 |
|
Yunsup Lee
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e7802825c3
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add Zscale testing
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2015-07-17 12:02:02 -07:00 |
|
Yunsup Lee
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4c7c3f5bb2
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add test generate for ZscaleTop
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2015-07-14 16:26:28 -07:00 |
|
Henry Cook
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76046c52fe
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Cleanup testing rv64uf
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2015-07-13 18:58:58 -07:00 |
|
Henry Cook
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302cd3e638
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Added BuildZscale param for use in Top and makefrag generation
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2015-07-13 15:46:42 -07:00 |
|
Henry Cook
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407d8e473e
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first cut at parameter-based testing
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2015-07-13 14:54:26 -07:00 |
|
Henry Cook
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4e4015089d
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rename Configs source
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2015-07-09 15:04:11 -07:00 |
|
Yunsup Lee
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09e29e8fe0
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add zscale
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
|
2015-07-07 20:38:47 -07:00 |
|
Yunsup Lee
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e6a13cdeba
|
New machine-mode timer facility
Mirroring Andrew's commit to reference-chip
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2015-07-07 17:26:07 -07:00 |
|
Henry Cook
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4fbb0f80ff
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Added some multicore/multibanks named ChiselConfigs
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2015-07-06 18:21:06 -07:00 |
|
Henry Cook
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d3ccec1044
|
Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
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2015-07-02 14:43:30 -07:00 |
|
Yunsup Lee
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702ddabe26
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add ExampleSmallConfig for README
|
2014-10-07 02:07:59 -07:00 |
|
Yunsup Lee
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e25d420155
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Improve ChiselConfig composability; bump chisel
|
2014-10-06 13:43:40 -07:00 |
|
Yunsup Lee
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73eac94a65
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Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays)
|
2014-10-06 13:40:35 -07:00 |
|
Henry Cook
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122733b3a9
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file name consistency
|
2014-10-06 13:37:38 -07:00 |
|
Henry Cook
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0b5f23a209
|
Streamlined uncore for release
|
2014-10-06 13:37:15 -07:00 |
|
Adam Izraelevitz
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15fb4730ec
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Add BuildTile parameter for Tile
Conflicts:
rocket
|
2014-09-25 06:50:45 -07:00 |
|
Henry Cook
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7398b00d93
|
dir supplied by function
|
2014-09-25 06:50:41 -07:00 |
|
Henry Cook
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5a840c5520
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support for multiple tilelink paramerterizations in same design
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2014-09-25 06:50:30 -07:00 |
|
Donggyu Kim
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eb384f6461
|
new RocketChipBackend implementation
|
2014-09-25 06:47:12 -07:00 |
|
Scott Beamer
|
f2ca887de3
|
better fpga configs
|
2014-09-25 06:47:03 -07:00 |
|
Donggyu Kim
|
4fe48f5a0a
|
bump chisel
|
2014-09-25 06:46:58 -07:00 |
|
Donggyu Kim
|
60d90f5230
|
recover collectNodesIntoComp in Backends.scala
|
2014-09-25 06:46:50 -07:00 |
|
Donggyu Kim
|
a53091b40f
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remove collectNodesIntoComp from Backends.scala
|
2014-09-25 06:46:27 -07:00 |
|
Scott Beamer
|
f4e6cd75ab
|
turn off fpu for default fpga config.
a larger fpga can use defaultconfig
|
2014-09-25 06:46:16 -07:00 |
|
Yunsup Lee
|
09de2e2794
|
compute number of outstanding misses for DRAMSideLLCNull
|
2014-09-12 18:09:38 -07:00 |
|
Yunsup Lee
|
1cfd9f5a0e
|
add LICENSE
|
2014-09-12 10:15:04 -07:00 |
|
Yunsup Lee
|
c98afa1fea
|
turn off DRAMSideLLC
|
2014-09-11 22:10:25 -07:00 |
|
Yunsup Lee
|
b5a64487eb
|
turn off DRAMSideLLC
|
2014-09-11 22:07:44 -07:00 |
|
Yunsup Lee
|
02c08a156f
|
generate consts.vh from chisel source
|
2014-09-10 17:14:55 -07:00 |
|