This proposal hasn't been adopted yet, but anything is better than the
current implementation, where clearing misa.C when the PC is misaligned
is effectively undefined.
In Rocket, debug triggers are supposed to happen before a store
occurs, rather than after. Previously, we reported the exception
on the store's PC, but the store occurred anyway. This probably
hasn't been problematic in practice because most stores are
idempotent.
- adds a mutable singleton (PlusArgArtefacts) to store information
about Rocket PlusArgs
- adds methods to PlusArgArtefacts to emit C snippets that are
consumed by emulator.cc for correct argument parsing and help text
generation
- emits snippets in $(CONFIG).plusArgs via BaseCoreplex-set
ElaborationArtefacts
- modify emulator/Makefrag-verilator to include $(CONFIG).plusArgs
- cleanup help text (docstring) for existing PlusArgs
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
When xLen > paddrBits, enforce that physical addresses are zero-extended.
This works by checking that the _virtual_ address is _sign_-extended, then
checking that its sign is positive.
* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
After detecting a corrupted BTB, don't speculatively update it until
the next non-speculative fetch. This prevents the frontend from replaying
forever.
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable. Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable. Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
Deallocation can change repl_way, which violates the assumption that it
remains constant throughout refill.
The workaround described in commit 3db066303b
still suffices, provided only the hart that owns the ITIM changes the ITIM
allocation.
This subsumes commit 3db066303b.
