 Andrew Waterman
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474d321cc7
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fix meta hazard counter to reset on new meta writes
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2013-05-01 16:35:24 -07:00 |
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Andrew Waterman
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a6a88fce19
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Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle"
This reverts commit b41e6bc50519631ba097ac1196737be7107295f9.
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2013-05-01 16:34:45 -07:00 |
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Andrew Waterman
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63a38e7982
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Revert "temp"
This reverts commit 73705e6ed8f98d08ce6b30fbe760de694c6563ae.
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2013-05-01 16:34:33 -07:00 |
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Andrew Waterman
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1501e90c1f
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interlock probe unit on tag RAW hazards
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2013-04-30 00:38:22 -07:00 |
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Andrew Waterman
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50ccc20bf3
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replace RDNPC with AUIPC
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2013-04-22 04:20:15 -07:00 |
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Andrew Waterman
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ae7720e284
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guarantee LR/SC forward progress
the mechanism is to block new probes for several cycles after a successful LR.
this also cleans up the MSHR <-> ProbeUnit interface slightly.
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2013-04-07 19:27:21 -07:00 |
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Andrew Waterman
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e74e032c87
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simplify MSHR memory response logic
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2013-04-06 01:03:37 -07:00 |
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Andrew Waterman
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1abb9277db
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fix LR/SC atomicity violation
note, it's still not starvation-free.
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2013-04-05 19:13:38 -07:00 |
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Andrew Waterman
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8cbdeb2abf
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add LR/SC support
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2013-04-04 17:07:09 -07:00 |
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Andrew Waterman
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fc46daecf6
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don't flush pipeline on writes to side-effect-free PCRs
notably, K0, K1, and EPC
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2013-04-04 17:07:09 -07:00 |
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Andrew Waterman
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8b439ef20d
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only support setpcr/clearpcr of SR
the full PCR RMW support was wasted area/power
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2013-04-04 17:07:08 -07:00 |
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Andrew Waterman
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d43f484feb
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take interrupts on nonzero fromhost values
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2013-04-04 17:07:08 -07:00 |
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Andrew Waterman
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d4a3351cfc
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expose pending interrupts in status register
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2013-04-04 17:07:08 -07:00 |
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Andrew Waterman
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35349d227f
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update to new Mem style
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2013-02-20 16:09:46 -08:00 |
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Andrew Waterman
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9f89c812b7
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fix HTIF memory size reporting
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2013-01-29 23:08:25 -08:00 |
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Andrew Waterman
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66eb3720a4
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fix SRAM semantics bug in HellaFlowQueue
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2013-01-29 21:16:42 -08:00 |
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Andrew Waterman
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6275e009f8
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fix HellaQueue deq.valid signal
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2013-01-28 20:57:43 -08:00 |
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Andrew Waterman
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45d8066f45
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add HellaQueue, an SRAM-based queue
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2013-01-28 20:54:25 -08:00 |
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Andrew Waterman
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37c67f1d87
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pipeline reset to the vector unit
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2013-01-28 17:56:32 -08:00 |
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Andrew Waterman
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c890099e09
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add System Control Register space to HTIF
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2013-01-24 23:41:24 -08:00 |
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Andrew Waterman
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575bd3445a
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re-generalize scoreboard
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2013-01-24 18:00:39 -08:00 |
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Andrew Waterman
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1fbc20450e
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don't allow simultaneous reads and writes to the tag ram
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2013-01-24 17:55:00 -08:00 |
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Andrew Waterman
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37ee843b2c
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don't use reset combinationally
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2013-01-24 17:55:00 -08:00 |
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Andrew Waterman
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bb6fbddf1f
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don't probe the mshr file to inquire about refills
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2013-01-24 17:54:59 -08:00 |
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Andrew Waterman
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5b9f938263
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correctly sign-extend badvaddr, epc, and ebase
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2013-01-24 17:54:59 -08:00 |
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Andrew Waterman
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667b4ee858
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remove Queue flush port (override reset instead)
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2012-08-22 13:39:19 -07:00 |
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Andrew Waterman
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d4a001b867
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add PriorityMux; use to implement PriorityEncoder
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2012-08-22 13:38:25 -07:00 |
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Andrew Waterman
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743e032f06
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generalize interface to DecodeLogic
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2012-08-22 13:38:07 -07:00 |
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Andrew Waterman
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80c243469e
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add flow queues and skid buffers
hopefully they work
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2012-07-30 18:47:12 -07:00 |
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Andrew Waterman
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2ec76390e3
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improve PriorityEncoderOH and add Counter util
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2012-07-30 16:06:55 -07:00 |
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Andrew Waterman
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7778802395
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reduce number of outstanding transactions
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2012-07-26 14:51:41 -07:00 |
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Andrew Waterman
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e496cd7584
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use Mem to implement queues to speed things up
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2012-07-13 21:48:05 -07:00 |
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Andrew Waterman
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bac82762d3
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use only one (wide) tag ram for set assoc. caches
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2012-07-12 14:50:12 -07:00 |
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Andrew Waterman
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429fcbed8e
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fix some LLC bugs
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2012-07-11 17:56:39 -07:00 |
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Andrew Waterman
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f645fb4dd7
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add L2$
It still has performance bugs but no correctness bugs AFAIK.
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2012-07-10 05:23:29 -07:00 |
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