Andrew Waterman
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bc15e8649e
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WIP on priv spec v1.9
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2016-03-02 23:29:58 -08:00 |
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Howard Mao
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120361226d
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fix more Chisel3 deprecations
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2016-01-14 14:46:31 -08:00 |
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Henry Cook
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4f8468b60f
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depend on external cde library
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2015-10-21 18:19:23 -07:00 |
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Henry Cook
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84576650b5
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Removed all traces of params
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2015-10-05 21:48:05 -07:00 |
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Andrew Waterman
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833909a2b5
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Chisel3 compatibility fixes
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2015-09-30 14:36:26 -07:00 |
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Andrew Waterman
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78b2e947de
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Chisel3 compatibility fixes
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2015-09-11 15:43:07 -07:00 |
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Andrew Waterman
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546205b174
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Chisel3 compatibility: use >>Int instead of >>UInt
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2015-08-05 15:29:03 -07:00 |
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Andrew Waterman
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57930e8a26
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Chisel3 compatibility potpourri
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2015-07-30 23:53:02 -07:00 |
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Andrew Waterman
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ce161b83e3
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Chisel3 compatibility: avoid subword assignment
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2015-07-29 15:03:13 -07:00 |
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Andrew Waterman
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ac6e73e317
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Add Wire() wrap
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2015-07-15 20:24:18 -07:00 |
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Andrew Waterman
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f460cb6c54
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Update to privileged architecture 1.7
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2015-05-19 02:32:21 -07:00 |
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Andrew Waterman
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bce62d5774
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Update PTE format to reflect reserved bits
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2015-04-04 15:19:15 -07:00 |
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Andrew Waterman
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d912ea265e
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New virtual memory implementation (Sv39)
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2015-03-27 16:20:59 -07:00 |
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Andrew Waterman
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0332c1e7fe
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Reduce latency of page table walks
A small cache in the PTW caches non-leaf PTEs, reducing latency and D$ misses.
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2015-03-24 18:58:38 -07:00 |
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Andrew Waterman
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e85c54cc4b
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New privileged ISA implementation
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2015-03-14 02:49:07 -07:00 |
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Christopher Celio
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06dea3790a
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Removed sret from ptw; sret now comes thru io.cpu to dcache
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2015-03-03 16:50:41 -08:00 |
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Henry Cook
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741e6b77ad
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Rename some params, use refactored TileLink
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2015-02-01 20:37:31 -08:00 |
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Yunsup Lee
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8abf62fae3
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add LICENSE
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2014-09-12 18:06:41 -07:00 |
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Henry Cook
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2de268b3b1
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Cache utility traits. Completely compiles, asm tests hang.
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2014-08-19 11:38:20 -07:00 |
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Henry Cook
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0dac9a7467
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Full conversion to params. Compiles but does not elaborate.
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2014-08-19 11:38:02 -07:00 |
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Andrew Waterman
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4ca152b012
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Use BundleWithConf to avoid clone method boilerplate
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2014-05-09 19:37:16 -07:00 |
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Henry Cook
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1fa505f9ff
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remove superfluous AVec object
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2014-04-16 17:19:32 -07:00 |
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Henry Cook
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910b3b203a
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removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
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2014-04-10 12:32:44 -07:00 |
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Andrew Waterman
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e8486817e6
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Clean up formatting (i.e. remove tabs, semicolons)
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2014-01-13 21:43:56 -08:00 |
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Andrew Waterman
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924261e2b2
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Update to new privileged ISA... phew
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2013-11-25 04:35:15 -08:00 |
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Henry Cook
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d06e24ac24
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new enum syntax
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2013-09-10 10:51:35 -07:00 |
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Andrew Waterman
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d4a0db4575
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Reflect ISA changes
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2013-08-24 14:43:55 -07:00 |
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Henry Cook
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3a266cbbfa
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final Reg changes
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2013-08-15 15:28:15 -07:00 |
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Henry Cook
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
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Henry Cook
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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Andrew Waterman
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8cbdeb2abf
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add LR/SC support
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2013-04-04 17:07:09 -07:00 |
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Henry Cook
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e1225c5114
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standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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Andrew Waterman
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90cae54ac4
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fix D$ read/write concurrency bug
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2012-11-27 02:42:27 -08:00 |
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Andrew Waterman
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9c857b83f0
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refactor PCR file
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2012-11-27 01:28:06 -08:00 |
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Andrew Waterman
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64674d4d39
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clean up PTW and support PADDR_BITS < VADDR_BITS
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2012-11-26 20:38:45 -08:00 |
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Andrew Waterman
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8dce89703a
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new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
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2012-11-16 02:39:33 -08:00 |
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Andrew Waterman
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4d1ca8ba3a
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remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
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2012-11-06 08:13:44 -08:00 |
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Andrew Waterman
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e76892f758
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remove more global constants
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2012-11-06 02:55:45 -08:00 |
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Andrew Waterman
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c5b93798fb
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factor out more global constants
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2012-11-05 23:52:32 -08:00 |
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Henry Cook
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88ac5af181
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Merged consts-as-traits
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2012-10-16 16:32:35 -07:00 |
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Andrew Waterman
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661f8e635b
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merge I$, ITLB, BTB into Frontend
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2012-10-16 02:24:37 -07:00 |
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Henry Cook
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5d2a470215
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all rocket-specific arbiters in one file and refactored traits slightly
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2012-10-15 16:05:32 -07:00 |
|
Henry Cook
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dfdfddebe8
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constants as traits
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2012-10-07 22:20:03 -07:00 |
|
Huy Vo
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fd95159837
|
INPUT/OUTPUT orderring swapped
|
2012-07-12 18:16:57 -07:00 |
|
Huy Vo
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04304fe788
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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Andrew Waterman
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e1f9dc2c1f
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generalize page table walker
also, don't instantiate vitlb when !HAVE_VEC
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2012-05-03 02:29:09 -07:00 |
|
Henry Cook
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622a801bb1
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Refactored cpu/cache interface to use nested bundles
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2012-05-02 11:54:28 -07:00 |
|
Andrew Waterman
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eafdffe125
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simplify page table walker; speed up emulator
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2012-05-01 01:24:36 -07:00 |
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Yunsup Lee
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62ada5ea9e
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hookup vitlb ptw port
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2012-03-17 23:01:06 -07:00 |
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Andrew Waterman
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6c26921766
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reduce D$ critical path through page table walker
costs an extra cycle per page table level to resolve a TLB miss. too bad.
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2012-03-16 18:35:54 -07:00 |
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