Wesley W. Terpstra
e034775bfa
tilelink2: use the fancy new hasData functions
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
11b0272d91
tilelink2: create optimized hasData method on edges (statically evaluates if known)
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
5db7ae262b
tilelink2: first version of Narrower (only supports uncached IO)
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
b004d54d71
tilelink2: add a Fragmenter adapter
...
God that was a pain in the ass!
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
ecc3c2a4b2
tilelink2: more efficient one-hot circuits
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
3d84795641
tilelink2: use LazyModule(new ...) just like Chisel Module(new ...)
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
2069ca5d8d
tilelink2: pass sourceInfo using implicits in Monitor
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
935b53f3bf
tilelink2: explicitly check that fixed fields never change in multibeat
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
e652cd155b
tilelink2: edge parameters on the same link had better match
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
c411a3e77f
tilelink2: simpler sizes requirement for users to understand
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
ab998c08f1
tilelink2: save some hardware in HintHandler if no BCE
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
18e7d4cd65
tilelink2: make it possible to write Node-only adapters
2016-09-05 20:58:40 -07:00
Wesley W. Terpstra
4a401fc480
tilelink2: add a Buffer adapter to insert pipeline stages
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
50f0dee69e
tilelink2: add an IdentityNode for adapters that change nothing
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
9cd2991fb3
tilelink2: AddressSet always has an assigned base address
...
The consensus seems to be that TileLink should not be assigning
addresses dynamically. The reasons:
1. We can come up with another scheme for assigning addresses that is
independent of TileLink. This decoupling is good, because it would
allow us to use the same mechanism for different buses in the SoC.
2. The informational flow of addresses is more likely to naturally follow
the module hierarchy than the TileLike bus topology. Thus, it seems
better to pass address parameterization using Module constructors.
3. Addresses are still checked by TileLink, so using a Module-centric
flow for addresses will not pose a correctness concern.
4. An address need only be provided to a slave on its construction and
TileLink parameterization spreads this globally. Thus, the burden to
manually assign an address is low.
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
ae2bc4da21
tilelink2: refactor RegField into interface and implementation
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
d6727abbbc
tilelink2: rename Operations to Edges (as it only includes Edges)
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
ee3e31cb23
tilelink2: refactor TLNodes into a seperate file
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
69b3de92a8
tilelink2: decouple BaseNode from TileLink bus (so it can be reused)
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
c785375276
tilelink2: use 'connect' instead of TL-specific 'tl' to connect nodes
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
05221d7073
tilelink2: rename Bases.scala to LazyModule.scala
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
8d54ae8508
tilelink2: move TL-specific stuff out of the LazyModule base classes
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
f99a3dbec7
tilelink2: rename Factory=>LazyModule and TLModule=>LazyModuleImp
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
5b31fb81fe
tilelink2: IDNode needs to be specialized for output vs. input passthrough
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
eac4d44131
tilelink2: don't apply HintHandler to B=>C by default
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
cc8112d02e
tilelink2: pass E through the HintHandler
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
a72f7115ae
tilelink2: optimize support testing circuits
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
f0cfd81820
tilelink2: add an adapter to add support for Hints to devices
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
5f6ca0bd0d
tilelink2: rename wmask => mask since it also applies to reads
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
7347b0c4dd
tilelink2: TLLegacy converts from legacy TileLink to TileLink2
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
fa472e38fb
tilelink2: monitor error line legality
2016-09-05 20:58:39 -07:00
Wesley W. Terpstra
edb17d1e34
tilelink2: document allowed (and required) response messages
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
ec1f901a38
tilelink2: move error from type into Bundle and add HintAck
...
We need Grant with errors too.
We also want to match response type to request type more easily.
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
534d7f6eb6
tilelink2: implement SRAM manager
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
32894a8e20
tilelink2: transfers must never exceed 4kB
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
dd27a60daa
tilelink2: use consistent in/out ports for TLSimpleFactories
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
1a87eef3e2
tilelink2: add atomic message types
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
5f7711a0c0
tilelink2: add an intermediate type for simple factories
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
967d8f108c
tilelink2: support ready-valid enqueue+dequeue on register fields
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
77cf186cf0
tilelink2: make bundle parameterization reusable
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
594850eaae
tilelink2: assert-fail on something more user understandable
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
dc1164a996
tilelink2: defer bundle construction until after Module base class instantiated
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
18e149098a
tilelink2: connect abstract register-based modules to TileLink
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
917a9c8e5d
tilelink2: forward declarations for message constructors
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
4649c42f50
tilelink2: use a new type in the signature of null-parameter Bundle methods
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
0ff33a31a4
tilelink2: add a stub SRAM manager
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
a87c2d13e2
tilelink2: include an abstract definition for register mapped devices
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
3a441d853f
tilelink2: clarify that fifoId only applies to accesses (not hints)
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
4b99bd3be1
tilelink2: mask out unnecessary address bits
2016-09-05 20:58:38 -07:00
Wesley W. Terpstra
e24ba61754
tilelink2: distinguish two levels of uncacheability
2016-09-05 20:58:38 -07:00
