1
0
Commit Graph

3044 Commits

Author SHA1 Message Date
Henry Cook
3d10a89907 refactor NASTI to not use param; new AddrMap class 2015-10-06 11:41:47 -07:00
Henry Cook
84576650b5 Removed all traces of params 2015-10-05 21:48:05 -07:00
Henry Cook
adcd77db36 Removed all traces of params 2015-10-05 20:33:55 -07:00
Henry Cook
970445a26a refactor MemIO to not use params 2015-10-02 15:37:41 -07:00
Henry Cook
69a4dd0a79 refactor NASTI to not use param 2015-10-02 14:20:47 -07:00
Henry Cook
39a749843c refactor NASTI to not use param; new AddrMap class 2015-10-02 14:19:51 -07:00
Andrew Waterman
c2ad0b7dd4 Unfuck fpga-zynq submodule pointer
Sorry, Scott.
2015-10-01 15:00:35 -07:00
Andrew Waterman
996670a4a6 Point to correct Chisel commit 2015-10-01 10:31:29 -07:00
Howard Mao
a76f0bf8fb fix involuntary release bug in rocket ProbeUnit 2015-09-30 17:26:48 -07:00
Howard Mao
19656e4abe make sure to generate release from clean coh state on probe miss 2015-09-30 16:58:18 -07:00
Andrew Waterman
8da7be3211 More Chisel3 compatibility fixes 2015-09-30 14:37:40 -07:00
Andrew Waterman
0fe16ac1c0 Chisel3 compatibility fixes 2015-09-30 14:37:00 -07:00
Andrew Waterman
833909a2b5 Chisel3 compatibility fixes 2015-09-30 14:36:26 -07:00
Andrew Waterman
a7c908cb83 Don't declare Reg inside of when
We haven't yet decided what the Chisel3 semantics for this will be.
2015-09-30 12:43:36 -07:00
Howard Mao
2f3d15675c fix DataArray writemask in L1D 2015-09-28 16:02:39 -07:00
Howard Mao
1e7f656527 get release block address from inner release 2015-09-28 15:02:51 -07:00
Andrew Waterman
79cdf6efc0 Make perf counters optional 2015-09-28 13:56:08 -07:00
Andrew Waterman
f8a7a80644 Make perf counters optional 2015-09-28 13:55:23 -07:00
Andrew Waterman
5e88ead984 Add pseudo-ops to instructions.scala 2015-09-28 11:52:27 -07:00
Andrew Waterman
b93a94597c Remove needless control logic 2015-09-27 13:31:52 -07:00
Howard Mao
353b00c8a1 revert some Chisel3-related changes and fix tlb bugs 2015-09-26 22:08:06 -07:00
Howard Mao
4bda6b6757 fix bug in tlb refill 2015-09-26 21:27:36 -07:00
Howard Mao
6bf8f41cef make sure passthrough requests are treated as vm_enabled = false 2015-09-26 20:29:51 -07:00
Howard Mao
c517d9f6e3 fix htif emulator constructor in vcs_main 2015-09-25 17:21:09 -07:00
Andrew Waterman
c3fff12ff0 Revert "replace remaining uses of Vec.fill"
This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
2015-09-25 17:09:06 -07:00
Andrew Waterman
3b1da4c57e Revert "replace remaining uses of Vec.fill"
This reverts commit b6bb4e42127d1ed42b55ec8b859a4e074b347d47.
2015-09-25 17:06:57 -07:00
Andrew Waterman
20b7a82ab6 Use Vec.fill, not Vec.apply, when making Vec literals 2015-09-25 17:06:52 -07:00
Andrew Waterman
a08872c0e9 val -> def in static object 2015-09-25 17:05:28 -07:00
Andrew Waterman
e75674c0cb Revert "replace remaining uses of Vec.fill"
This reverts commit 16dca2186b95945ad2ba5f906113101de0726617.
2015-09-25 17:05:07 -07:00
Andrew Waterman
2179cb64ae Let isRead be true for store-conditional
This works around a deadlock bug in the L1 D$, and is arguably true.
2015-09-25 15:28:02 -07:00
Andrew Waterman
0bfb2962a6 Assume coh.isRead returns true for store-conditional
This requires an uncore update.
2015-09-25 15:26:11 -07:00
Howard Mao
7b0167b92e make sure SCR and PCR data width matches xLen 2015-09-25 12:13:22 -07:00
Howard Mao
0e67d824b4 fix NASTI interconnect bug 2015-09-25 12:12:34 -07:00
Howard Mao
308022210a use updated NASTI channel constructors 2015-09-25 12:07:27 -07:00
Howard Mao
8c4ac0f4f3 make sure CSR/SCR data width matches xLen 2015-09-25 12:07:03 -07:00
Howard Mao
a9c6cced2d fix bug in NASTIArbiter 2015-09-25 11:03:24 -07:00
Howard Mao
2e63fb291a put sensible defaults for NASTI channel constructors 2015-09-25 10:09:25 -07:00
Howard Mao
0d763524ef make sure conf address map scales with number of cores 2015-09-25 09:41:19 -07:00
Howard Mao
5e3f9115d3 make sure HTIF mem_mb doesn't exceed MMIOBase 2015-09-25 09:02:35 -07:00
Schuyler Eldridge
f200d0947a Force C++ emulator to always use 1GB for MEM_SIZE
Fixes #17
2015-09-24 23:56:41 -04:00
Howard Mao
c20ed350a0 even more Chisel3 compatability changes 2015-09-24 17:55:41 -07:00
Howard Mao
a66bdb1956 replace remaining uses of Vec.fill 2015-09-24 17:53:26 -07:00
Howard Mao
88b15dba60 replace remaining uses of Vec.fill 2015-09-24 17:51:38 -07:00
Howard Mao
d1f2d40a90 replace remaining uses of Vec.fill 2015-09-24 17:50:09 -07:00
Howard Mao
3ff830e118 ReorderQueue uses Vec of Bools instead of Bits for roq_free 2015-09-24 17:43:53 -07:00
Howard Mao
1c0111cc70 uncore merge commit 2015-09-24 17:10:45 -07:00
Howard Mao
83740dfaa5 Merge branch 'master' of github.com:ucb-bar/uncore 2015-09-24 17:10:09 -07:00
Howard Mao
8d4d8680bf replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:59:13 -07:00
Howard Mao
4a85c5a510 pull in hardfloat fixes 2015-09-24 16:58:49 -07:00
Howard Mao
3b86790c3f replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:58:20 -07:00