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3e6dc35809
|
issue self-probes for uncached read transactions
this facilitates I$ coherence. but it seems like a hack and perhaps
the mechanism should be rethought.
|
2012-11-16 02:37:56 -08:00 |
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0cd0f8a9db
|
Initial version of migratory protocol
|
2012-10-23 18:01:53 -07:00 |
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2aecb0024f
|
UncoreConfiguration now contains coherence policy
|
2012-10-18 16:57:28 -07:00 |
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ffda0e41a9
|
parameterize width of MemSerdes/MemDesser
|
2012-10-18 16:56:36 -07:00 |
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9df5cfa552
|
Factored out tilelink classes
|
2012-10-16 14:26:33 -07:00 |
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8509cda813
|
Refined traits for use with rocket asserts, added UncoreConfiguration to handle ntiles
|
2012-10-16 13:58:18 -07:00 |
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1418604bf0
|
new constants organization
|
2012-10-15 18:52:48 -07:00 |
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08ab076217
|
forgot to change package + using fromBits in memserdes instead of manual unpacking
|
2012-10-10 15:42:39 -07:00 |
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9610622ab0
|
moving memserdes + slowio into src
|
2012-10-10 12:41:11 -07:00 |
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35f213e735
|
Merge branch 'master' of ../rocket-clone
|
2012-10-10 12:39:48 -07:00 |
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3973aef938
|
handle structural hazard on LLC tags
|
2012-10-09 18:04:55 -07:00 |
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916c1019af
|
fixed memdessert unpacking
|
2012-10-09 13:03:17 -07:00 |
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cf8f20584e
|
factoring out uncore into separate uncore repo
|
2012-10-01 16:08:41 -07:00 |
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2413763f3d
|
henry's uncore and rocket changes for new xact types
|
2012-10-01 16:05:37 -07:00 |
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da6ec486f1
|
uncore and rocket changes for new xact types
|
2012-10-01 10:47:36 -07:00 |
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fa8075570a
|
move srcs into src dir, factoring out uncore consts into consts
|
2012-09-27 12:59:45 -07:00 |
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6546dc84e2
|
rename queue to Queue
fixes build with case-insensitive file system
|
2012-08-08 22:11:59 -07:00 |
|
|
|
aa7fd1f40b
|
rename queue to Queue
fixes build with case-insensitive file system
|
2012-08-08 22:11:59 -07:00 |
|
|
|
17dc2075dd
|
fix some LLC control bugs
|
2012-08-06 17:10:04 -07:00 |
|
|
|
115c25c34b
|
fix some LLC control bugs
|
2012-08-06 17:10:04 -07:00 |
|
|
|
875f3622af
|
fix deadlock in coherence hub
|
2012-08-03 19:00:03 -07:00 |
|
|
|
962423d2d1
|
fix deadlock in coherence hub
|
2012-08-03 19:00:03 -07:00 |
|
|
|
e346f21725
|
fix control bug in LLC
structural hazard on tag ram caused deadlock
|
2012-08-03 18:59:37 -07:00 |
|
|
|
92b7504c9a
|
fix control bug in LLC
structural hazard on tag ram caused deadlock
|
2012-08-03 18:59:37 -07:00 |
|
|
|
7a75334bb9
|
pipeline LLC further
|
2012-07-31 17:45:14 -07:00 |
|
|
|
7b9cfd0b90
|
pipeline LLC further
|
2012-07-31 17:45:14 -07:00 |
|
|
|
8db233c9b7
|
further pipeline the LLC
|
2012-07-30 20:12:11 -07:00 |
|
|
|
85dc34df80
|
further pipeline the LLC
|
2012-07-30 20:12:11 -07:00 |
|
|
|
4d4e28c138
|
remove reset pin on llc
|
2012-07-28 21:14:51 -07:00 |
|
|
|
914b6b622d
|
remove reset pin on llc
|
2012-07-28 21:14:51 -07:00 |
|
|
|
465f2efca7
|
add reset pin to llc
|
2012-07-27 18:44:39 -07:00 |
|
|
|
0a2d284d24
|
add reset pin to llc
|
2012-07-27 18:44:39 -07:00 |
|
|
|
1ae3091261
|
memory system bug fixes
|
2012-07-26 00:05:21 -07:00 |
|
|
|
1405718ca8
|
memory system bug fixes
|
2012-07-26 00:05:21 -07:00 |
|
|
|
7736405726
|
fix bug in coherence hub, respect xact_rep.ready
|
2012-07-23 20:56:55 -07:00 |
|
|
|
d0e12c13f6
|
fix bug in coherence hub, respect xact_rep.ready
|
2012-07-23 20:56:55 -07:00 |
|
|
|
df8aff0906
|
don't dequeue probe queue during reset
|
2012-07-22 21:05:52 -07:00 |
|
|
|
c6ac836581
|
don't dequeue probe queue during reset
|
2012-07-22 21:05:52 -07:00 |
|
|
|
d01e70c672
|
decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
|
2012-07-17 22:55:40 -07:00 |
|
|
|
0258dfb23f
|
decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
|
2012-07-17 22:55:40 -07:00 |
|
|
|
a79747a062
|
INPUT/OUTPUT orderring swapped
|
2012-07-12 18:16:57 -07:00 |
|
|
|
18bc14058b
|
INPUT/OUTPUT orderring swapped
|
2012-07-12 18:16:57 -07:00 |
|
|
|
62a3ea4113
|
fix some LLC bugs
|
2012-07-11 17:56:39 -07:00 |
|
|
|
0aa33bf909
|
fix some LLC bugs
|
2012-07-11 17:56:39 -07:00 |
|
|
|
1ebfeeca8a
|
add L2$
It still has performance bugs but no correctness bugs AFAIK.
|
2012-07-10 05:23:29 -07:00 |
|
|
|
66cf690261
|
add L2$
It still has performance bugs but no correctness bugs AFAIK.
|
2012-07-10 05:23:29 -07:00 |
|
|
|
166b857055
|
ioDecoupled -> FIFOIO, ioPipe -> PipeIO
|
2012-06-06 18:22:56 -07:00 |
|
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|
0c6bade592
|
ioDecoupled -> FIFOIO, ioPipe -> PipeIO
|
2012-06-06 18:22:56 -07:00 |
|
|
|
9b3161920f
|
moving util out into Chisel standard library
|
2012-06-06 12:51:26 -07:00 |
|
|
|
f2942f79f9
|
moving util out into Chisel standard library
|
2012-06-06 12:51:26 -07:00 |
|
