riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
1ebfeeca8a
rocket-chip/uncore
History
Andrew Waterman 1ebfeeca8a add L2$ 
It still has performance bugs but no correctness bugs AFAIK.
2012-07-10 05:23:29 -07:00
..
llc.scala add L2$ 2012-07-10 05:23:29 -07:00
memserdes.scala ioDecoupled -> FIFOIO, ioPipe -> PipeIO 2012-06-06 18:22:56 -07:00
slowio.scala ioDecoupled -> FIFOIO, ioPipe -> PipeIO 2012-06-06 18:22:56 -07:00
uncore.scala ioDecoupled -> FIFOIO, ioPipe -> PipeIO 2012-06-06 18:22:56 -07:00