1a87eef3e2
tilelink2: add atomic message types
2016-09-05 20:58:38 -07:00
5f7711a0c0
tilelink2: add an intermediate type for simple factories
2016-09-05 20:58:38 -07:00
967d8f108c
tilelink2: support ready-valid enqueue+dequeue on register fields
2016-09-05 20:58:38 -07:00
77cf186cf0
tilelink2: make bundle parameterization reusable
2016-09-05 20:58:38 -07:00
594850eaae
tilelink2: assert-fail on something more user understandable
2016-09-05 20:58:38 -07:00
dc1164a996
tilelink2: defer bundle construction until after Module base class instantiated
2016-09-05 20:58:38 -07:00
18e149098a
tilelink2: connect abstract register-based modules to TileLink
2016-09-05 20:58:38 -07:00
917a9c8e5d
tilelink2: forward declarations for message constructors
2016-09-05 20:58:38 -07:00
4649c42f50
tilelink2: use a new type in the signature of null-parameter Bundle methods
2016-09-05 20:58:38 -07:00
0ff33a31a4
tilelink2: add a stub SRAM manager
2016-09-05 20:58:38 -07:00
a87c2d13e2
tilelink2: include an abstract definition for register mapped devices
2016-09-05 20:58:38 -07:00
3a441d853f
tilelink2: clarify that fifoId only applies to accesses (not hints)
2016-09-05 20:58:38 -07:00
4b99bd3be1
tilelink2: mask out unnecessary address bits
2016-09-05 20:58:38 -07:00
e24ba61754
tilelink2: distinguish two levels of uncacheability
2016-09-05 20:58:38 -07:00
e506309998
tilelink2: prototype crossbar implementation
2016-09-05 20:58:37 -07:00
34f65938b6
tilelink2: add a TLBundle constructor
2016-09-05 20:58:37 -07:00
1cd85ff050
tilelink2: add some bundle introspection to scaffold the xbar
2016-09-05 20:58:37 -07:00
9c62f5d9c1
tilelink2: shave off a few more firrtl monitor lines
2016-09-05 20:58:37 -07:00
af29595979
tilelink2: eliminate common subexpressions in Monitor to reduce firrtl output
2016-09-05 20:58:37 -07:00
d7e839280f
tilelink2: include legal message monitor
2016-09-05 20:58:37 -07:00
492a38aedc
tilelink2: only accesses can have errors (release must make forward progress)
2016-09-05 20:58:37 -07:00
6599bcb77b
tilelink2: statically check Operations are remotely plausible
2016-09-05 20:58:37 -07:00
8cff45f254
tilelink2: use byte-aligned addressing
...
This makes it possible to fully validate user input in a monitor.
We will override the lower bits with constant 0s in the TL connect.
2016-09-05 20:58:37 -07:00
45e152e97e
tilelink2: include Operation constructors
2016-09-05 20:58:37 -07:00
5b10c1a328
tilelink2: arithmetic and logical atomics must be distinct (priv spec 3.5.3)
2016-09-05 20:58:37 -07:00
8592cbf0e3
tilelink2: Message and Permisison types from Henry
2016-09-05 20:58:37 -07:00
9a460322da
tilelink2: add synthesizable test methods for Parameters
2016-09-05 20:58:37 -07:00
7328b55abd
tilelink2: first cut at parameterization
2016-09-05 20:58:37 -07:00
59a2e6a4dc
Merge pull request #244 from ucb-bar/compelete-dramsim-removal
...
remove remaining dramsim2 files
2016-09-05 15:05:38 -07:00
ba4b3e14cc
remove remaining dramsim2 files
2016-09-04 17:25:24 -07:00
8906097250
have Travis cache the entire verilator directory
2016-09-04 15:05:30 -07:00
a7f79aa409
get rid of TileLinkMemorySelector
2016-09-04 10:55:19 -07:00
f0ab6d0214
tie off finish signals in tilelink wrapper and unwrapper
2016-09-04 10:55:19 -07:00
66de89c4db
allow fixed priority routing in Junctions arbiters
2016-09-04 10:55:19 -07:00
efe8670283
allow Serializer/Deserializer to work with arbitrary Chisel data types
2016-09-04 10:55:19 -07:00
b9b79e4fb6
get rid of AtoS RTL
2016-09-04 10:55:19 -07:00
f34843f1b9
fix assignment of incoherent vector
2016-09-04 10:12:16 -07:00
a4c1942958
flatten Coreplex module hierarchy
2016-09-02 17:45:08 -07:00
63679bb019
Add support for L1 data scratchpads instead of caches
...
They fit in the same part of the address space as DRAM would be, and
are coherent (because they are not cacheable).
They are currently limited to single cores without DRAM. We intend
to lift both restrictions, probably when we add support for
heterogeneous tiles.
2016-09-02 16:22:07 -07:00
dc9ae19936
Work-around for current Scala compiler "structural type loses implicits".
...
Running rocket-chip through the chisel3 gsdt branch which supports stricter connection checks and uses implicit definitions to deal with "old" direction overrides, exposed a possible bug in the Scala compiler.
[error] .../src/main/scala/uncore/devices/Prci.scala:27: value asOutput is not a member of uncore.devices.PRCIInterrupts{val mtip: chisel3.core.Bool; val msip: chisel3.core.Bool}
[error] possible cause: maybe a semicolon is missing before `value asOutput'?
[error] }.asOutput
[error] ^
[error] one error found
[error] (uncore/compile:compileIncremental) Compilation failed
This change isn't strictly required for current chisel3 code, but is being submitted in anticipation of an eventual merge of the gsdt branch prior to a compiler fix.
2016-09-02 15:38:18 -07:00
fb50f7c9dd
Set default TileLink width to XLen
2016-09-02 15:27:54 -07:00
e23e4d6de5
Add ClientUncachedTileLinkEnqueuer utility
2016-09-02 15:27:54 -07:00
7aeb42fa55
Allow narrow TL interface on PRCI; make mtime writable
2016-09-02 15:27:54 -07:00
6872000f5e
Merge pull request #239 from ucb-bar/move_rtc
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Move RTC
2016-09-02 15:17:49 -07:00
af364bc7bc
Rename RTC to RTCTick to clarify that it needs to be a Boolean signal, not a Clock type signal
2016-09-02 15:14:39 -07:00
8163a6b597
Make it easier to override the 'placeholder' Real-Time-Clock, to allow more real-world applications
2016-09-02 11:11:40 -07:00
c05ba1e864
Add TileId parameter, generalizing GroundTestId
...
This usually shouldn't be used in Tiles that are meant to be P&R'd once
and multiply instantiated, as their RTL would no longer be homogeneous.
However, it is useful for conditionalizing RTL generation for
heterogeneous tiles.
2016-09-02 00:10:50 -07:00
4a7972be31
connect testharness components via member functions ( #236 )
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to prevent code duplication for new testbenches
2016-09-01 18:38:39 -07:00
08089f695d
allow configuration to be in separate project from test harness
2016-09-01 10:28:07 -07:00
c66318307c
no longer need to set invalidate_lr in RoCC examples
2016-08-31 22:05:35 -07:00
