riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
5,189 Commits 1 Branch 0 Tags 13 MiB
329a5c35d4
Commit Graph

91 Commits

Author SHA1 Message Date
Andrew Waterman
568bfa6c50 Purge legacy HTIF things 
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
 2016-06-23 13:23:57 -07:00
Howard Mao
daa0f3038f invoke firrtl jar directly in order to control heap memory usage 2016-06-20 13:02:31 -07:00
Palmer Dabbelt
e6c4372332 Fix "make run-asm-tests" for Chisel 3 
This was just a missing Makefrag-verilog dependency (the .d file).
 2016-06-06 21:36:55 -07:00
Wesley W. Terpstra
da566e7d6a build: use local sbt when building firrtl 2016-05-25 11:48:03 -07:00
Andrew Waterman
e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
Howard Mao
18ffe7b1ec don't use +verbose in vsim .run rule 2016-05-04 23:01:14 -07:00
Andrew Waterman
46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
Andrew Waterman
1f211b37df WIP on new memory map 2016-04-27 14:57:54 -07:00
Andrew Waterman
46d7dceb1e Disable printf/assert during reset 2016-04-01 18:18:08 -07:00
Howard Mao
c831a0a4e5 use scala firrtl instead of stanza firrtl 2016-03-30 19:35:25 -07:00
Howard Mao
c081a36893 Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter" 
This reverts commit 5378f79b50.
 2016-03-30 19:06:32 -07:00
jackkoenig
5378f79b50 Bump chisel3 and firrtl, add support for firrtl $ delimiter 2016-03-29 20:16:07 -07:00
Palmer Dabbelt
cddfdf0929 Add CHISEL_VERSION make argument 
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3.  Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
 2016-03-24 12:00:13 -07:00
Palmer Dabbelt
7c0c48fac4 Resurrect the backup memory port 
We need this to work for our chip, and it's not been tested in a long
time in upstream -- it didn't even used to build since the Nasti
conversion.  This makes a few changes:

 * Rather than calling the backup memory port parameters MEM_*, it calls
   them MIF_* (to match the MIT* paramater objects).  A new name was
   necessary because the Nasti stuff is now dumped as MEM_*, which has
   similar names but incompatible values.

 * p(MIFDataBits) was changed back to 128, as otherwise the backup
   memory port doesn't work (it only send half a TileLink transaction).
   64 also causes readmemh to bail out, but changing the elf2hex parameters
   works around that.

 * A configuration was added that enabled the backup memory port in the
   tester.  While this is kind of an awkward way to do it, I want to
   make sure I can start testing this regularly and this makes it easy to
   integrate.
 2016-02-27 10:46:56 -08:00
Palmer Dabbelt
db9de94588 Generate and use SCR address header files 
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
 2016-02-17 15:23:18 -08:00
Andrew Waterman
e0d849fec5 Fix zscale testing 
Use the following command in vsim:

make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
 2015-12-01 17:31:48 -08:00
Palmer Dabbelt
07f0e6be94 Don't re-generate the .d files on "make clean" 2015-11-12 00:41:55 -08:00
Yunsup Lee
1e772daeea no spaces in Makefrag 2015-11-05 16:42:05 -08:00
Howard Mao
bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc add multichannel NASTI support in Verilog testbench 2015-11-05 10:48:32 -08:00
Henry Cook
9769b2747c now depend on external cde library rather than chisel.params (bump all submodules) 2015-10-21 18:24:16 -07:00
Christopher Celio
83df4bcc35 Fixed run-bmark-tests make target in vsim 2015-09-09 22:37:47 -07:00
Henry Cook
d21ffa4dba Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used 2015-07-28 00:24:07 -07:00
Yunsup Lee
a99b1e3a01 append config name to generated Makefrag filename 2015-07-17 12:34:49 -07:00
Yunsup Lee
e7802825c3 add Zscale testing 2015-07-17 12:02:02 -07:00
Yunsup Lee
d6df479870 move 'include /Makefrag' out of top-level Makefrag 2015-07-14 16:13:32 -07:00
Henry Cook
407d8e473e first cut at parameter-based testing 2015-07-13 14:54:26 -07:00
Henry Cook
d3ccec1044 Massive update containing several months of changes from the now-defunct private chip repo. 
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
 2015-07-02 14:43:30 -07:00
Schuyler Eldridge
b4cd8c5981 Fix vlsi_mem_gen for Python 2 or 3 2015-06-25 12:48:31 -07:00
Yunsup Lee
70b0f9fd4d error out for PCWM-L, port width mismatch 2014-09-25 06:50:50 -07:00
Yunsup Lee
221007595b allow BACKEND/CONFIG be environment variables 2014-09-17 11:12:08 -07:00
Yunsup Lee
1cfd9f5a0e add LICENSE 2014-09-12 10:15:04 -07:00
Yunsup Lee
275b72368b add CONFIG to the name of simulator executable 2014-09-11 22:11:58 -07:00
Yunsup Lee
5f8bd18fac Makefiles should be perfect 2014-09-11 02:53:46 -07:00
Yunsup Lee
02c08a156f generate consts.vh from chisel source 2014-09-10 17:14:55 -07:00
Yunsup Lee
cfecd8832d tease out reference-chip specific stuff 2014-09-09 20:49:28 -07:00
Yunsup Lee
ddfd3ce968 further generalize fpga/vlsi builds 2014-09-08 00:21:57 -07:00
Yunsup Lee
1cb2d1d7b7 initialize all SRAMs to avoid X propagation problem 2014-09-04 11:06:01 -07:00
Yunsup Lee
763c57931b fix problem introduced with verilog generation in vsim/fsim 2014-09-04 09:49:57 -07:00
Scott Beamer
6c6f5a3843 add verilog target to build without simulator 2014-09-03 17:28:45 -07:00
Yunsup Lee
c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00