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rocket-chip/vsim
Palmer Dabbelt db9de94588 Generate and use SCR address header files
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
..
.gitignore update for rocket-chip release 2014-08-31 20:26:55 -07:00
Makefile Don't re-generate the .d files on "make clean" 2015-11-12 00:41:55 -08:00
Makefrag Generate and use SCR address header files 2016-02-17 15:23:18 -08:00
Makefrag-verilog add multichannel NASTI support in Verilog testbench 2015-11-05 10:48:32 -08:00
vlsi_mem_gen Massive update containing several months of changes from the now-defunct private chip repo. 2015-07-02 14:43:30 -07:00