add CONFIG to the name of simulator executable

vsim/Makefile

@@ -23,6 +23,9 @@ include $(sim_dir)/Makefrag
 include $(base_dir)/vsim/Makefrag-sim
 
 all: $(simv)
+debug: $(simv_debug)
 
 clean:
 	rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)
+
+.PHONY: default all debug clean

vsim/Makefrag

@@ -5,9 +5,9 @@
 # Verilog sources
 
 sim_vsrcs = \
-	$(generated_dir)/$(MODEL).v \
-	$(generated_dir)/consts.vh \
-	$(generated_dir)/memdessertMemDessert.v \
+	$(generated_dir)/$(MODEL).$(CONFIG).v \
+	$(generated_dir)/consts.$(CONFIG).vh \
+	$(generated_dir)/memdessertMemDessert.$(CONFIG).v \
 	$(base_dir)/vsrc/rocketTestHarness.v \
 	$(base_dir)/vsrc/backup_mem.v \
 
@@ -50,12 +50,12 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet
 # Build the simulator
 #--------------------------------------------------------------------
 
-simv = $(sim_dir)/simv
+simv = $(sim_dir)/simv-$(CONFIG)
 $(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
 	cd $(sim_dir) && \
 	$(VCS) $(VCS_OPTS) -o $(simv) \
 
-simv_debug = $(sim_dir)/simv-debug
+simv_debug = $(sim_dir)/simv-$(CONFIG)-debug
 $(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
 	cd $(sim_dir) && \
 	$(VCS) $(VCS_OPTS) -o $(simv_debug) \