fix problem introduced with verilog generation in vsim/fsim

vsim/Makefile

@@ -15,11 +15,11 @@ vlsi_mem_gen = $(base_dir)/vsim/vlsi_mem_gen
 sim_dir = .
 output_dir = $(sim_dir)/output
 
-include $(sim_dir)/Makefrag
 include $(base_dir)/Makefrag
+include $(sim_dir)/Makefrag
 include $(base_dir)/vsim/Makefrag-sim
 
 all: $(simv)
 
 clean:
-	rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)/*
+	rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)

vsim/Makefrag

@@ -19,6 +19,14 @@ sim_csrcs = \
 	$(base_dir)/csrc/mm.cc \
 	$(base_dir)/csrc/mm_dramsim2.cc \
 
+#--------------------------------------------------------------------
+# Build Verilog
+#--------------------------------------------------------------------
+
+verilog: $(sim_vsrcs)
+
+.PHONY: verilog
+
 #--------------------------------------------------------------------
 # Build rules
 #--------------------------------------------------------------------