Henry Cook
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d06e24ac24
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new enum syntax
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2013-09-10 10:51:35 -07:00 |
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Stephen Twigg
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cfbfa6b895
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Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits.
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2013-09-05 19:22:34 -07:00 |
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Stephen Twigg
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d896ccbd43
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Merge branch 'master' into chisel-v2
Conflicts:
src/main/scala/htif.scala
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2013-09-05 16:11:53 -07:00 |
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Andrew Waterman
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b9f6e1a7ec
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Don't update BTB when garbage was fetched
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2013-08-26 14:53:04 -07:00 |
|
Yunsup Lee
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44e92edf92
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fix scr parameterization bug
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2013-08-24 22:42:51 -07:00 |
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Andrew Waterman
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3895b75a56
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Support non-power-of-2 BTBs; prefer invalid entries
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2013-08-24 17:33:11 -07:00 |
|
Yunsup Lee
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2ca5127785
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parameterize number of SCRs
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2013-08-24 15:47:14 -07:00 |
|
Andrew Waterman
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daf23b8f79
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Add early out to multiplier
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2013-08-24 14:44:23 -07:00 |
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Andrew Waterman
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67f80ba4b2
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Stall div/mul writeback until WB slot is free
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2013-08-24 14:44:17 -07:00 |
|
Andrew Waterman
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d1b5076fee
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Don't update BTB when garbage was fetched
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2013-08-24 14:44:11 -07:00 |
|
Andrew Waterman
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52e31f3298
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Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
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2013-08-24 14:44:04 -07:00 |
|
Andrew Waterman
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d4a0db4575
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Reflect ISA changes
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2013-08-24 14:43:55 -07:00 |
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Henry Cook
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ff7b486006
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standardized sbt build
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2013-08-15 18:13:19 -07:00 |
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Henry Cook
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ae02ebd153
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Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2
Conflicts:
src/core.scala
src/ctrl.scala
src/dpath_util.scala
src/fpu.scala
src/nbdcache.scala
src/tile.scala
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2013-08-15 16:35:27 -07:00 |
|
Henry Cook
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3a266cbbfa
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final Reg changes
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2013-08-15 15:28:15 -07:00 |
|
Henry Cook
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b570435847
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Reg standardization
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2013-08-13 17:50:02 -07:00 |
|
Henry Cook
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858169917e
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removed dummy DNCs handled by pruning
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2013-08-12 22:34:46 -07:00 |
|
Henry Cook
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d9b3c7cfc8
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Moved RenEn to ChiselUtil
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2013-08-12 22:18:25 -07:00 |
|
Huy Vo
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387cf0ebe0
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reset -> resetVal, getReset -> reset
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2013-08-12 20:51:54 -07:00 |
|
Henry Cook
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
|
Henry Cook
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de313d97de
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2013-08-02 16:30:09 -07:00 |
|
Henry Cook
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4eaab214d2
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:29:51 -07:00 |
|
Henry Cook
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bef6c1db35
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minor nbdcache cleanup
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2013-08-02 16:29:37 -07:00 |
|
Stephen Twigg
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3132db4f90
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Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity.
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2013-07-30 16:36:28 -07:00 |
|
Henry Cook
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
|
Henry Cook
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5c00d0a030
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new tilelink arbiter type
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2013-07-09 15:31:46 -07:00 |
|
Andrew Waterman
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7cc53c7725
|
clean up Str
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2013-06-15 00:45:53 -07:00 |
|
Andrew Waterman
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95c5147dc5
|
Add RISC-V instruction disassembler
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2013-06-13 10:31:04 -07:00 |
|
Henry Cook
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569d8fd796
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Merge branch 'tilelink-data'
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2013-05-23 14:14:40 -07:00 |
|
Henry Cook
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12205b9684
|
remove obsolete config file reader prototype
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2013-05-23 14:09:03 -07:00 |
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Andrew Waterman
|
fe9adfe71b
|
Simplify and correct integer multiplier
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2013-05-22 17:27:50 -07:00 |
|
Yunsup Lee
|
11133d6d4c
|
clock gate s2 registers in the frontend
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2013-05-21 18:59:21 -07:00 |
|
Yunsup Lee
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c837c1d800
|
fix bug in previous JALR commit
on commit tag 9a122c06d1bf11237d7fb0769d454a67bbb7400e
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2013-05-21 18:28:44 -07:00 |
|
Henry Cook
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69b508ff39
|
ported caches and htif to use new tilelink
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2013-05-21 17:21:04 -07:00 |
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Andrew Waterman
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28f914c3f2
|
don't JALR to speculatively-bypassed addresses
Technically not necessary, but probably improves performance.
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2013-05-21 16:56:58 -07:00 |
|
Yunsup Lee
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dcde377303
|
Fix DM I$ deadlock
BTB predictions were causing infinite miss loops
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2013-05-20 15:22:58 -07:00 |
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Andrew Waterman
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3a1b5f01b2
|
don't take interrupts while they're disabled!
a control bug allowed an interrupt to be taken on the instruction immediately
following an interrupt-disabling instruction (but not thereafter).
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2013-05-19 23:27:47 -07:00 |
|
Andrew Waterman
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6eb4c2542a
|
comment out I$ assert for now
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2013-05-18 18:09:23 -07:00 |
|
Andrew Waterman
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1dab984231
|
use UFix instead of Bits for arithmetic
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2013-05-18 00:45:29 -07:00 |
|
Andrew Waterman
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dfa7a03f73
|
use assert, not Assert
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2013-05-18 00:45:13 -07:00 |
|
Andrew Waterman
|
d405ffa949
|
assume all I$ grants bear data
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2013-05-01 21:01:20 -07:00 |
|
Andrew Waterman
|
474d321cc7
|
fix meta hazard counter to reset on new meta writes
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2013-05-01 16:35:24 -07:00 |
|
Andrew Waterman
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a6a88fce19
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Revert "broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle"
This reverts commit b41e6bc50519631ba097ac1196737be7107295f9.
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2013-05-01 16:34:45 -07:00 |
|
Andrew Waterman
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63a38e7982
|
Revert "temp"
This reverts commit 73705e6ed8f98d08ce6b30fbe760de694c6563ae.
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2013-05-01 16:34:33 -07:00 |
|
Henry Cook
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b6945408cb
|
temp
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2013-05-01 10:24:36 -07:00 |
|
Henry Cook
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722bc917d3
|
broaden scope of s1_nack to include new probes accepted by the probe unit on that cycle
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2013-05-01 10:05:54 -07:00 |
|
Andrew Waterman
|
1501e90c1f
|
interlock probe unit on tag RAW hazards
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2013-04-30 00:38:22 -07:00 |
|
Henry Cook
|
e8b20f3d38
|
clear meta state of silently-dropped, clean evictee, so as to prevent a write race on meta array between probes on evictee and refill grant
|
2013-04-25 17:41:04 -07:00 |
|
Andrew Waterman
|
50ccc20bf3
|
replace RDNPC with AUIPC
|
2013-04-22 04:20:15 -07:00 |
|
Henry Cook
|
db5a060c7d
|
fix io dir
|
2013-04-10 13:47:30 -07:00 |
|
Andrew Waterman
|
ae7720e284
|
guarantee LR/SC forward progress
the mechanism is to block new probes for several cycles after a successful LR.
this also cleans up the MSHR <-> ProbeUnit interface slightly.
|
2013-04-07 19:27:21 -07:00 |
|
Andrew Waterman
|
e74e032c87
|
simplify MSHR memory response logic
|
2013-04-06 01:03:37 -07:00 |
|
Andrew Waterman
|
1abb9277db
|
fix LR/SC atomicity violation
note, it's still not starvation-free.
|
2013-04-05 19:13:38 -07:00 |
|
Andrew Waterman
|
8cbdeb2abf
|
add LR/SC support
|
2013-04-04 17:07:09 -07:00 |
|
Andrew Waterman
|
fc46daecf6
|
don't flush pipeline on writes to side-effect-free PCRs
notably, K0, K1, and EPC
|
2013-04-04 17:07:09 -07:00 |
|
Andrew Waterman
|
8b439ef20d
|
only support setpcr/clearpcr of SR
the full PCR RMW support was wasted area/power
|
2013-04-04 17:07:08 -07:00 |
|
Andrew Waterman
|
d43f484feb
|
take interrupts on nonzero fromhost values
|
2013-04-04 17:07:08 -07:00 |
|
Andrew Waterman
|
d4a3351cfc
|
expose pending interrupts in status register
|
2013-04-04 17:07:08 -07:00 |
|
Henry Cook
|
f8aebcbf8c
|
fix for cache controller bug: failing to mux correct metadata into mshr.io.old_meta on tag match
|
2013-04-04 15:50:29 -07:00 |
|
Henry Cook
|
16113a96ba
|
fixes after merge
|
2013-03-25 19:09:08 -07:00 |
|
Henry Cook
|
95f0a688e9
|
Merge branch 'release-xacts'
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
|
2013-03-20 17:37:50 -07:00 |
|
Henry Cook
|
273bd34091
|
Generalized mem arbiter, moved to uncore. Support for multiple banks when acking grants.
|
2013-03-20 15:53:36 -07:00 |
|
Henry Cook
|
6d2541aced
|
nTiles -> nClients in LogicalNetworkConfig
|
2013-03-20 14:12:36 -07:00 |
|
Andrew Waterman
|
ea9d0b771e
|
remove aborts; simplify probes
|
2013-03-19 15:29:40 -07:00 |
|
Yunsup Lee
|
0f50970913
|
move HellaQueue to uncore
|
2013-03-19 00:43:20 -07:00 |
|
Henry Cook
|
e0361840bd
|
writebacks on release network pass asm tests and bmarks
|
2013-02-28 18:11:40 -08:00 |
|
Andrew Waterman
|
35349d227f
|
update to new Mem style
|
2013-02-20 16:09:46 -08:00 |
|
Andrew Waterman
|
9f89c812b7
|
fix HTIF memory size reporting
|
2013-01-29 23:08:25 -08:00 |
|
Yunsup Lee
|
a0bd0adeb2
|
change write/read port ordering for vlsi_mem_gen script
|
2013-01-29 21:32:42 -08:00 |
|
Andrew Waterman
|
66eb3720a4
|
fix SRAM semantics bug in HellaFlowQueue
|
2013-01-29 21:16:42 -08:00 |
|
Yunsup Lee
|
60bd3a6413
|
Revert "shuffled FPU control logic around to make functional unit retiming work better"
This reverts commit 20dd308067b143adff4913fc7ac710a393ca1d86.
|
2013-01-29 19:34:55 -08:00 |
|
Andrew Waterman
|
6275e009f8
|
fix HellaQueue deq.valid signal
|
2013-01-28 20:57:43 -08:00 |
|
Andrew Waterman
|
45d8066f45
|
add HellaQueue, an SRAM-based queue
|
2013-01-28 20:54:25 -08:00 |
|
Andrew Waterman
|
37c67f1d87
|
pipeline reset to the vector unit
|
2013-01-28 17:56:32 -08:00 |
|
Rimas Avizienis
|
f2df6147df
|
shuffled FPU control logic around to make functional unit retiming work better
|
2013-01-28 17:17:09 -08:00 |
|
Henry Cook
|
f5729c9f25
|
removed ack_required field from grant messages
|
2013-01-28 16:44:17 -08:00 |
|
Henry Cook
|
8cbd316b5e
|
Merge branch 'ready-sig-fix' into pin-cleanup
|
2013-01-27 23:04:58 -08:00 |
|
Henry Cook
|
931cffa749
|
ready signal fix
|
2013-01-27 23:04:35 -08:00 |
|
Henry Cook
|
83c207c852
|
pin cleanup in htif
|
2013-01-27 12:00:28 -08:00 |
|
Henry Cook
|
409b549d3c
|
actually cleared up tile ios
|
2013-01-27 11:27:09 -08:00 |
|
Henry Cook
|
696dd102eb
|
cleans up unconnected tile io pins (networking headers overwritten at top level)
|
2013-01-27 10:59:41 -08:00 |
|
Andrew Waterman
|
c890099e09
|
add System Control Register space to HTIF
|
2013-01-24 23:41:24 -08:00 |
|
Andrew Waterman
|
575bd3445a
|
re-generalize scoreboard
|
2013-01-24 18:00:39 -08:00 |
|
Andrew Waterman
|
1fbc20450e
|
don't allow simultaneous reads and writes to the tag ram
|
2013-01-24 17:55:00 -08:00 |
|
Andrew Waterman
|
37ee843b2c
|
don't use reset combinationally
|
2013-01-24 17:55:00 -08:00 |
|
Andrew Waterman
|
bb6fbddf1f
|
don't probe the mshr file to inquire about refills
|
2013-01-24 17:54:59 -08:00 |
|
Andrew Waterman
|
5b9f938263
|
correctly sign-extend badvaddr, epc, and ebase
|
2013-01-24 17:54:59 -08:00 |
|
Rimas Avizienis
|
63060bc0a8
|
minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
|
2013-01-23 19:27:53 -08:00 |
|
Henry Cook
|
6b00e7ff74
|
New TileLink bundle names
|
2013-01-21 17:18:23 -08:00 |
|
Henry Cook
|
a2fa3fd04d
|
Refactored packet headers/payloads
|
2013-01-15 15:50:37 -08:00 |
|
Henry Cook
|
e1225c5114
|
standardize IO naming convention
|
2013-01-07 13:41:36 -08:00 |
|
Henry Cook
|
261e14f831
|
Refactored uncore conf
|
2013-01-07 13:41:36 -08:00 |
|
Andrew Waterman
|
78868f6075
|
add config option to trade mul/div area for speed
|
2013-01-06 03:47:17 -08:00 |
|
Andrew Waterman
|
ce9f4881d2
|
remove broken multiplier early out
|
2013-01-06 03:47:00 -08:00 |
|
Andrew Waterman
|
05f19b21d0
|
merge multiplier and divider
|
2012-12-12 02:22:47 -08:00 |
|
Andrew Waterman
|
c921fc34a9
|
merge ALU left and right shifters
|
2012-12-12 02:22:34 -08:00 |
|
Andrew Waterman
|
f5c53ce35d
|
add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
|
2012-12-11 15:58:53 -08:00 |
|
Andrew Waterman
|
3f59e439ef
|
fix d$ tag raw hazard
|
2012-12-07 15:14:20 -08:00 |
|
Andrew Waterman
|
e9752f1d72
|
pipeline host pcr access
|
2012-12-06 14:22:07 -08:00 |
|
Andrew Waterman
|
4dda38204f
|
fix d$ reset bug
|
2012-12-06 03:13:22 -08:00 |
|