riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
3,269 Commits 1 Branch 0 Tags 13 MiB
2979badf75
Commit Graph

3269 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
roman3017
2979badf75 Update README.md 
Fixed path to Configs.scala
 2016-09-12 18:55:14 -07:00
Colin Schmidt
a10d058e1a fix warnings in verilog source (#274) 2016-09-12 18:25:35 -07:00
Andrew Waterman
88440ebf89 Use PseudoLRU in BTB when possible (for powers of two) 2016-09-12 16:52:03 -07:00
Andrew Waterman
266a2f24bd Disable Mul early out by default if XLen == 32 
With a default unroll of 8, it doesn't help performance, but costs area.
 2016-09-12 16:50:08 -07:00
Andrew Waterman
96185e4b16 tighten an assert condition 
dcache.s1_kill is a don't-care if dcache.req.valid wasn't previously high
 2016-09-12 16:49:46 -07:00
Andrew Waterman
beb141a20b Allow M, A, D, C extensions to be disabled in misa register 2016-09-12 16:49:46 -07:00
Andrew Waterman
e66abb5e92 Merge pull request #276 from ucb-bar/nmemchannels-fix 
Pass nMemChannels to coreplex through CoreplexConfig
 2016-09-12 14:05:50 -07:00
Howard Mao
f3cdeb08c6 pass nMemChannels to coreplex through CoreplexConfig 2016-09-12 12:40:10 -07:00
Howard Mao
9d9f90646d allow configuration of simulation memory latency 2016-09-12 12:33:50 -07:00
Andrew Waterman
49bba961cf Merge pull request #259 from ucb-bar/refactor-periphery 
Refactor Periphery
 2016-09-12 12:18:00 -07:00
Yunsup Lee
d985cdfc66 Merge branch 'master' into refactor-periphery 2016-09-10 23:42:13 -07:00
Yunsup Lee
fea31c7061 let GlobalAddrMap and ConfigString overridable 2016-09-10 23:39:44 -07:00
Yunsup Lee
bb3f514e8d now able to add periphery devices through traits 
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
 2016-09-10 23:39:29 -07:00
mwachs5
395bc16da6 Merge pull request #271 from ucb-bar/black_box_regs_fix 
Get rid of the unecessary Parameters for Async Reset Reg
 2016-09-10 14:14:12 -07:00
Megan Wachs
77e4aa63f8 Get rid of the unecessary Parameters for Async Reset Reg 2016-09-09 16:24:35 -07:00
Andrew Waterman
e6889ea711 Merge pull request #269 from ucb-bar/tweaks 
Two tweaks to Rocket perf & QoR
 2016-09-09 15:25:15 -07:00
Andrew Waterman
b695ab5292 Merge branch 'master' into tweaks 2016-09-09 15:04:21 -07:00
mwachs5
8273ca1ae7 Merge pull request #265 from ucb-bar/black_box_regs 
Make it possible to have Async Reset Flops
 2016-09-09 13:54:04 -07:00
Megan Wachs
5f5989848c Merge remote-tracking branch 'origin/master' into black_box_regs 2016-09-09 13:12:52 -07:00
Colin Schmidt
cf3c6fa277 add STOP_COND to emulator & match vsim PRINTF_COND 2016-09-09 11:07:17 -07:00
Andrew Waterman
656aa78f7d Pipeline FMAs more deeply by default 
Rocket's QoR has improved enough that the FMAs are on the critical
path.  This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
 2016-09-09 11:06:42 -07:00
Andrew Waterman
eaa4b04ee5 Check D$ store->load collisions more precisely 
Tolerate, for example, a half-word store and a half-word load to
different halves of the same word.
 2016-09-09 11:06:42 -07:00
Henry Cook
c4593d2034 Merge pull request #266 from ucb-bar/multinode 
TL2Node: make it possible for {Identity,Output,Input}Node to pass a Vec
 2016-09-09 10:17:45 -07:00
Wesley W. Terpstra
c28ca37944 tilelink2: get rid of fragile implicit lazyModule pattern, and support := 
We can more reliably find the current LazyModule from the LazyModule.stack
 2016-09-08 23:06:59 -07:00
Wesley W. Terpstra
b587a409a3 tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec 
In order to implement a pass-through RAM Monitor model, we will want to support
a variable number of inputs and outputs with BOTH different manager and client
parameters on each bundle.
 2016-09-08 21:34:20 -07:00
Yunsup Lee
176f385b1d Merge pull request #263 from ucb-bar/intbar 
TL2 Interrupts
 2016-09-08 21:33:25 -07:00
Wesley W. Terpstra
48ca478578 Merge branch 'master' into intbar 2016-09-08 21:09:59 -07:00
Wesley W. Terpstra
808a7f60f4 tilelink2 Legacy: it's only an error if it's valid (#264) 2016-09-08 21:09:40 -07:00
Megan Wachs
fda4c2bd76 Add a way to create Async Reset Registers and a way to easily access them with TL2 2016-09-08 20:02:07 -07:00
Megan Wachs
c1eb1f12a2 tilelink2: Rename GPIO to Example to avoid conflicts with real GPIO devices 2016-09-08 20:02:07 -07:00
Wesley W. Terpstra
cbf0670156 tilelink2 Legacy: it's only an error if it's valid 2016-09-08 19:32:00 -07:00
Wesley W. Terpstra
1b07d53f70 tilelink2 IntNodes: record interrupt ranges in parameters 2016-09-08 18:51:43 -07:00
Richard Xia
9015276958 Use sbt-launch.jar 0.13.12. (#262) 2016-09-08 17:26:04 -07:00
Wesley W. Terpstra
66f58cf2d0 tilelink2 RegisterRouter: support new TL2 interrupts 2016-09-08 15:25:50 -07:00
Wesley W. Terpstra
23e896ed5d tilelink2 IntNodes: support interrupt graphs 2016-09-08 15:25:48 -07:00
Wesley W. Terpstra
d7df7d3109 tilelink2: connect Nodes to LazyModules for better error messages 2016-09-08 15:24:04 -07:00
Wesley W. Terpstra
53987cd9d4 tilelink2 Nodes: support non-Bundle data for io type 2016-09-08 15:19:12 -07:00
Henry Cook
a44fff5d93 Merge pull request #260 from ucb-bar/w1ToClear 
W1 to clear
 2016-09-08 14:27:03 -07:00
Wesley W. Terpstra
60a503dc2f tilelink2 RegField: add a w1ToClear RegField 2016-09-08 14:02:49 -07:00
Wesley W. Terpstra
99b7e734cd tilelink2 Bundles: fix wrong sink width! 2016-09-08 13:47:40 -07:00
Wesley W. Terpstra
9bfd8c1cf5 TL2 WidthWidget (#258) 
* tilelink2 Narrower: support widenening and narrowing on all channels

Be extra careful with the mask transformations

We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.

* tilelink2 SRAM: work around firrtl SeqMem bug

* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)

* tilelink2 mask: fix an issue with width=1 data buses
 2016-09-08 10:38:38 -07:00
Yunsup Lee
2c000a99da compartmentalize Top into periphery traits 2016-09-08 02:08:57 -07:00
Yunsup Lee
8536a2a47d Merge pull request #257 from ucb-bar/fix-non-contiguous-mmio-region-routing 
Fix routing in non-contiguous MMIO regions
 2016-09-08 00:03:11 -07:00
Howard Mao
62e33527d3 Merge branch 'master' into fix-non-contiguous-mmio-region-routing 2016-09-07 23:35:12 -07:00
Howard Mao
4592558047 Merge pull request #254 from ucb-bar/inferRW 
Turn on the inferRW Firrtl pass
 2016-09-07 21:59:05 -07:00
Yunsup Lee
e35e7b2ee3 Fix routing in non-contiguous MMIO regions 
This is a temporary fix, which can generate more hardware than necessary, but this is OK for now, since this code will soon be replaced with tilelink2 code.
 2016-09-07 19:28:12 -07:00
Ben Keller
6be569be9f Turn on the inferRW Firrtl pass 
Without this, all of the memories wind up as two-ported.
 2016-09-07 15:27:26 -07:00
Howard Mao
7a6f155b2a Merge pull request #253 from ucb-bar/use-companion 
only use companion objects for types
 2016-09-07 15:07:17 -07:00
Andrew Waterman
7603b86239 Merge branch 'master' into use-companion 2016-09-07 12:56:55 -07:00
Andrew Waterman
58c87bdf32 Merge pull request #245 from ucb-bar/tilelink2.2 
Tilelink2
 2016-09-07 12:56:22 -07:00