Howard Mao
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dd1fed41b6
|
generate BootROM contents from assembly code
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2016-08-05 16:39:21 -07:00 |
|
Howard Mao
|
9fa5b228b2
|
allow extra devices and top-level ports to be added without changing RocketChip.scala
|
2016-08-04 14:06:14 -07:00 |
|
Howard Mao
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410e3e5366
|
make sure TraceGen gets correct addresses
|
2016-08-04 11:08:25 -07:00 |
|
Howard Mao
|
0a85e92652
|
Allow additional internal MMIO devices to be created without changing BaseConfig
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2016-08-04 11:04:52 -07:00 |
|
Howard Mao
|
f04aefc95c
|
get rid of deprecated ZynqAdapter
|
2016-08-02 13:14:20 -07:00 |
|
Howard Mao
|
63b814fcd7
|
only run the important (high coverage) tests in regression suite
|
2016-08-02 10:54:05 -07:00 |
|
Howard Mao
|
b7723f1ff8
|
make unit tests local to the packages being tested
|
2016-08-01 17:02:00 -07:00 |
|
Howard Mao
|
98eede0505
|
some refactoring in RocketChip top-level
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2016-08-01 17:02:00 -07:00 |
Megan Wachs
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55c992bb3a
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Use FoldRight() instead of for loop
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2016-08-01 16:56:33 -07:00 |
|
Megan Wachs
|
8db2e8829f
|
Allow aggregate CONFIG on Command Line
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2016-08-01 14:24:16 -07:00 |
Andrew Waterman
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fe670e5421
|
Stop using deprecated FileSystemUtilities to create files
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2016-07-31 18:04:56 -07:00 |
|
Andrew Waterman
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058396aefe
|
[rocket] Implement RVC
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2016-07-29 17:56:42 -07:00 |
|
Howard Mao
|
cb86aaa46b
|
fix trace generator addresses
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2016-07-28 17:56:14 -07:00 |
|
Howard Mao
|
ecd1af326c
|
fix L2 deadlock bug and add more advanced trace generator
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2016-07-26 12:43:08 -07:00 |
|
Howard Mao
|
1063d90993
|
make sure L1 and L2 agree on coherence policy
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2016-07-25 12:20:49 -07:00 |
|
Howard Mao
|
6a5b2d7f59
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fix assembly tests for configurations without VMU and/or user mode
|
2016-07-22 17:21:57 -07:00 |
|
Howard Mao
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75347eed56
|
some fixes and cleanup to stateless bridge
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2016-07-21 19:51:26 -07:00 |
|
Megan Wachs
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c31c650def
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If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge.
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2016-07-21 13:54:28 -07:00 |
|
Howard Mao
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20df74d138
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generate more L1 voluntary releases in TraceGen
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2016-07-21 12:33:55 -07:00 |
Wesley W. Terpstra
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9ae23f18bd
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rocket: support asynchronous external busses
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2016-07-19 14:52:56 -07:00 |
|
Howard Mao
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e08ec42bc0
|
refactor groundtest unittests into separate package
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2016-07-16 23:19:55 -07:00 |
|
Megan Wachs
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407bc95c42
|
Rename MulDivUnroll to MulUnroll
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2016-07-15 15:40:17 -07:00 |
|
Megan Wachs
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4c26a6bc96
|
Create seperate Mul/Div paramters instead of UseFastMulDiv
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2016-07-15 14:40:37 -07:00 |
|
Andrew Waterman
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ba08255450
|
bump rocket
|
2016-07-14 22:11:19 -07:00 |
|
Andrew Waterman
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768403f8fa
|
Bump rocket; remove ICacheBufferWays parameter
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2016-07-14 12:50:16 -07:00 |
|
Howard Mao
|
90bcd3dbdc
|
make sure DirectGroundTest testers given correct TL settings
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2016-07-11 18:11:01 -07:00 |
|
Howard Mao
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8f0fa11ce4
|
optionally export detailed status information in DirectGroundTest
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2016-07-11 18:11:00 -07:00 |
|
Howard Mao
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cb2a18b533
|
allow direct instatiation of arbitrary non-caching groundtests
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2016-07-11 18:11:00 -07:00 |
|
Howard Mao
|
f03ffb32a0
|
add top that directly tests the TL -> AXI converters
|
2016-07-11 18:11:00 -07:00 |
|
Howard Mao
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b47f8fbc41
|
don't use splat and bug out if too many address map entries
|
2016-07-11 18:10:42 -07:00 |
|
Wesley W. Terpstra
|
46fc9744e2
|
rocket: add an AXI master port into the chip
|
2016-07-11 12:16:44 -07:00 |
|
Wesley W. Terpstra
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8ac7fa5544
|
ext: support multiple external AHB/AXI ports
|
2016-07-11 12:16:39 -07:00 |
|
Howard Mao
|
9ec55ebb91
|
don't add io:ext region to address map if no external MMIO
|
2016-07-08 15:29:35 -07:00 |
|
Howard Mao
|
35547aa428
|
allow NastiConverterTest and Memtest to run simultaneously
|
2016-07-08 13:40:52 -07:00 |
|
Howard Mao
|
358668699f
|
refactoring groundtest configuration
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2016-07-08 11:40:16 -07:00 |
|
Howard Mao
|
eeac405ef8
|
get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache
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2016-07-08 09:33:07 -07:00 |
|
Andrew Waterman
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32ee5432dd
|
Fix testing of DefaultSmallConfig; bump rocket et al
|
2016-07-07 21:23:49 -07:00 |
|
Howard Mao
|
8c13e78ab5
|
add buffering and locking to TL -> AXI converter
|
2016-07-06 16:57:09 -07:00 |
|
Howard Mao
|
e27cb5f885
|
fix voluntary release issue in L2 cache
|
2016-07-06 16:57:01 -07:00 |
|
Howard Mao
|
f79a3285fb
|
fix TraceGen and Nasti -> TL converter
|
2016-07-05 17:42:57 -07:00 |
|
Howard Mao
|
c924ec2a22
|
fixing bufferless broadcast hub
|
2016-07-05 12:10:22 -07:00 |
|
Howard Mao
|
b01871c3de
|
test configurations for both shrinking and growing TL -> MIF
|
2016-07-01 18:13:33 -07:00 |
|
Howard Mao
|
e04e3d2571
|
make TestBench generator handle different top module names
|
2016-07-01 10:53:08 -07:00 |
|
Howard Mao
|
600f2da38a
|
export TL interface for Mem/MMIO and fix TL width adapters
|
2016-06-30 18:20:43 -07:00 |
|
Howard Mao
|
74cd588c65
|
refactor uncore to split into separate packages
|
2016-06-28 14:10:25 -07:00 |
|
Andrew Waterman
|
c725a78086
|
Merge RTC into PRCI
|
2016-06-27 23:08:29 -07:00 |
|
Howard Mao
|
d10fc84a8b
|
no longer require caching interfaces for groundtest tiles
|
2016-06-27 17:32:49 -07:00 |
|
Howard Mao
|
2dd8d90ae4
|
make Comparator fit the GroundTest model
|
2016-06-27 16:01:32 -07:00 |
|
Andrew Waterman
|
568bfa6c50
|
Purge legacy HTIF things
The SCR file is gone, too, because it was tightly coupled. The
general concept could be revived as a module that somehow connects
to the debug module.
|
2016-06-23 13:23:57 -07:00 |
|
Andrew Waterman
|
2d44be747a
|
Fix groundtest without HTIF
|
2016-06-23 12:17:26 -07:00 |