1b6fa70b5c
Add test for external TL clients (bus mastering)
2016-08-18 14:26:03 -07:00
ed827678ac
Write test harness in Chisel
...
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected). However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary. Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.
This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence. The main blocker is the lack of Verilog parameterization for
BlackBox. It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL. But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
38e0967816
strip DMA and RoCC CSRs out of rocket and uncore ( #201 )
2016-08-15 23:08:55 -07:00
458520c8f6
Use a generic UInt for TileLink op sizes, rather than MT_xx enum
2016-08-09 15:24:51 -07:00
b7723f1ff8
make unit tests local to the packages being tested
2016-08-01 17:02:00 -07:00
832e56d3c7
Fix toBits/toUInt/toSInt deprecation warnings
2016-07-31 17:13:52 -07:00
2891eb879a
add MergedPutRegression to uncover merged put after release bug in L2
2016-07-29 16:42:28 -07:00
064020bdd7
make sure Memtest generators write different data to each address
2016-07-29 14:22:46 -07:00
5a3beca097
add RepeatedGetRegression to uncover L2 merged get miss bug
2016-07-28 19:58:47 -07:00
cb86aaa46b
fix trace generator addresses
2016-07-28 17:56:14 -07:00
bd5972503f
move groundtest/scripts to top-level scripts/
2016-07-28 11:36:55 -07:00
0bd7ef1278
re-enable SCs inflight with other requests
2016-07-26 22:21:41 -07:00
df07771fa0
add uncached noise generator to TraceGen
2016-07-26 22:21:10 -07:00
24ef4e6dea
make sure to use AND not OR for combining finished signals
2016-07-21 12:05:11 -07:00
d77d0ddc5d
rename CacheTest.scala to CacheFillTest.scala
2016-07-20 20:37:45 -07:00
d56362f04c
add configuration checks for TraceGen
2016-07-20 10:37:10 -07:00
959630630a
give LCG an inc signal and add object constructors
2016-07-20 10:36:28 -07:00
b013925ab0
make sure ReleaseRegression starts only on io.start
2016-07-19 15:42:45 -07:00
577c73667b
use getSimpleName to dump out test names
2016-07-19 14:42:58 -07:00
1dac2930eb
fix bug in WriteMaskedPutBlockRegression
2016-07-19 14:42:23 -07:00
bc39d52655
changes to multi-transaction timer
2016-07-18 18:26:18 -07:00
359252fdc1
fix a width bug
2016-07-18 09:33:17 -07:00
6fc4236782
add atomic and prefetch drivers
2016-07-18 09:33:17 -07:00
2ec736ed67
reorder some code in the Nasti unit tests
2016-07-18 09:33:17 -07:00
3ea299b062
make unit test debug output more meaningful
2016-07-18 09:33:17 -07:00
def740406c
fix a few Driver bugs
2016-07-18 09:33:17 -07:00
8278a73e83
group unit tests by their tested interface
2016-07-18 09:33:17 -07:00
9c0fffdd1c
start constructing composable tilelink unit test drivers
2016-07-18 09:33:17 -07:00
c92732dcaa
rename MemoryTestDriver to NastiDriver
2016-07-18 09:33:16 -07:00
c906e6edde
some renaming
2016-07-18 09:33:16 -07:00
1c2bf6e938
make list of unit tests a a parameter
2016-07-18 09:33:16 -07:00
69eebaf362
factor out unit tests into separate package
2016-07-18 09:33:16 -07:00
4af6313288
TraceGen: Lookup -> MuxLookup
...
A recent commit to tracegen.scala introduced a call to BitPat() which
seems to mess up the subsequent call to Lookup(). (This function
seems undocumented so I'm not sure what's going on.) As a fix, I've
removed the call to BitPat() and replaced Lookup() with MuxLookup().
2016-07-17 22:28:18 +01:00
f3775df04d
fix the condition under which comparator error signal is set
2016-07-12 18:37:13 -07:00
88dc0b983a
make sure Comparator logs correctly when prefetching off
2016-07-12 14:36:46 -07:00
676a536706
fix bugs from adding ComparatorSource backpressure
2016-07-12 13:50:34 -07:00
d435bb4185
reduce hardware usage of Comparator to allow it to synthesize
2016-07-12 10:54:18 -07:00
18967642de
export more detailed status data from GroundTest
2016-07-11 16:41:55 -07:00
e194677087
fix comparator PutBlock data generation and debug output
2016-07-11 12:15:37 -07:00
5a3d6a1583
NastiTest should cycle through write ids
2016-07-08 17:55:02 -07:00
d80c2f480f
make NastiConverterTest act as generator and share blocks
2016-07-08 13:39:46 -07:00
850fa092a4
refactor how groundtests are configured
2016-07-08 11:40:01 -07:00
f62c74b82a
allow groundtest to use non-blocking DCache
2016-07-07 18:59:09 -07:00
67871654dd
start NastiConverterTest higher up in memory
2016-07-07 14:35:04 -07:00
9f7845f043
don't test BRAMSlave for now
2016-07-06 16:56:14 -07:00
8625f9ea0c
Update PTE format
2016-07-06 03:20:41 -07:00
ee624b1c6e
make NastiSmallTest a bit more intensive
2016-07-05 17:31:51 -07:00
8c5fd86f9b
fix tracegen module and scripts
2016-07-05 13:50:17 -07:00
61a44dcfc3
add regression test for L1 voluntary releases
2016-07-04 17:02:24 -07:00
7f0a583515
timeout for Nasti tests
2016-07-01 18:11:44 -07:00
