riscv/rocket-chip
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Author SHA1 Message Date
Henry CookandGitHub 1bfdfacda0 Merge pull request #1234 from grebe/bindFixup 
Use bind from global namespace
 2018-02-09 15:59:51 -08:00
Henry CookandGitHub 9a56221566 Merge pull request #1192 from seldridge/auto-plusargs 
Automatic PlusArg for emulator.cc
 2018-02-08 18:29:31 -08:00
Henry CookandGitHub fe277cf6f0 Merge branch 'master' into auto-plusargs 2018-02-06 18:38:44 -08:00
Henry CookandGitHub ad58b37437 Merge pull request #1215 from freechipsproject/config-altermap 
Misc updates to Config and Generator APIs
 2018-01-31 14:22:17 -08:00
Henry CookandAndrew Waterman b1fa19e801 bump hardfloat for scala 2.11.12 (#1216) 2018-01-30 20:42:36 -08:00
Henry Cook 7dad486707 util: updates to internal Generator API 2018-01-30 15:19:37 -08:00
Henry Cook bd50a1a4bc config: remove deprecated Parameters.root 2018-01-30 11:52:44 -08:00
Henry Cook 46751bedeb config: MapParameters are back in style 2018-01-30 11:52:44 -08:00
Henry CookandGitHub 5cc1411e14 Merge pull request #1199 from freechipsproject/require-messages 
rocket: add address to tlb permissions require msgs
 2018-01-18 14:53:25 -08:00
Henry Cook 24c1235500 rocket: add address to tlb permissions require msgs 2018-01-18 10:31:51 -08:00
Henry CookandGitHub f5211765e9 Merge pull request #1177 from freechipsproject/dont-touch-2 
Make more use of chisel3.experimental.DontTouch
 2018-01-09 15:13:55 -08:00
Henry Cook 15c54b1c5a tile: intSinkNode belongs in HasExternalInterrupts 2018-01-08 19:38:10 -08:00
Henry Cook 11e5b620f8 tile: disable more monitors on slave port 2018-01-08 18:42:25 -08:00
Henry Cook 5075a93e6c util: dontTouch work-around for zero width aggregates 2018-01-08 15:58:28 -08:00
Henry CookandGitHub 4fd4ae38e3 Merge pull request #1176 from freechipsproject/fix-tl-port 
Fix TL MMIO port
 2018-01-05 20:37:44 -08:00
Henry CookandGitHub 3525489fff Merge pull request #1174 from freechipsproject/error-device-tracked 
Claim that ErrorDevice is TRACKED
 2018-01-05 17:17:22 -08:00
Henry Cook b77b93b0b4 util: dontTouchPortsExcept 2018-01-05 14:06:00 -08:00
Henry Cook 4853d1355f rocket: dontTouch HellaCache.io.cpu.resp 2018-01-05 12:50:24 -08:00
Henry Cook 847efde385 coreplex: dontTouch the tile_inputs wire 2018-01-05 12:47:41 -08:00
Henry CookandGitHub 1bd343bcef Merge pull request #1156 from freechipsproject/has-tiles 
coreplex: make HasTiles more generic
 2018-01-02 19:38:17 -08:00
Henry Cook 320900f76c tile: BaseTileModule => BaseTileModuleImp 2018-01-02 17:55:54 -08:00
Henry Cook b0e1bc3071 tile: cake reduction 
* merge HasScratchpadSlavePort into RocketTile
* merge CanHaveSharedFPUModule into BaseTileModule
 2018-01-02 17:49:08 -08:00
Henry Cook efe7165b54 tile: BaseTile refactor, pt 2 
* 2 layer cake
* no more bundle traits, only call to IO
 2018-01-02 15:37:31 -08:00
Henry Cook 1579ddb97e tile: removed RocketTileWrapper. RocketTile now HasCrossing. 2017-12-28 14:00:13 -08:00
Henry Cook 1cd018546c tile: BaseTile refactor, pt 1 
* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
 2017-12-26 11:04:15 -08:00
Henry Cook ba6dd160a3 diplomacy: allow access to sram Device info 2017-12-22 19:00:43 -08:00
Henry Cook d9c5ec4f7b coreplex: HasTiles supplies def tileParams 2017-12-20 17:18:55 -08:00
Henry Cook ddaeedf2d0 coreplex: make HasTiles more generic 
HasTiles now deals with only extremely general tile IOs.
Some RocketTiles specific behavior moved into RocketCoreplex.
BaseTile now has optional LocalInterruptNode.
 2017-12-20 17:18:55 -08:00
Henry CookandGitHub 9b82f1098d Merge pull request #1154 from freechipsproject/bump-sbt 
Bump chisel, firrtl, and sbt
 2017-12-19 14:16:47 -08:00
Henry CookandGitHub 895c4b9261 Revert "ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144)" (#1162) 
This reverts commit a542ae687e.
 2017-12-19 12:16:26 -08:00
Henry CookandGitHub a31ba2ea2e diplomacy: LazyModule factory uses ValName (#1159) 
* diplomacy: LazyModule factory uses ValName
 2017-12-18 15:40:30 -08:00
Henry CookandGitHub 71ddd797bf Merge pull request #1138 from freechipsproject/cover_tag_ecc_error_during_fence_i 
Added coverage point to cover the case when ECC error happens during …
 2017-12-01 18:00:11 -08:00
Henry CookandGitHub bab0b99d7a Merge pull request #1131 from freechipsproject/fix-dcache-tag-ecc-error-under-flush 
Avoid data corruption under correctable tag error during flush
 2017-11-30 12:27:15 -08:00
Henry CookandGitHub 9e0c26f855 Merge pull request #1118 from freechipsproject/basic-bus-blocker-3 
tile: bus blocker needs to know width
 2017-11-17 21:57:20 -08:00
Henry Cook f3575404c0 tile: bus blocker needs to know width :( 2017-11-17 20:17:17 -08:00
Henry CookandGitHub b625e68360 tile: put a BasicBusBlocker inside RocketTile (#1115) 
...instead of on the master side of the system bus.

People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
 2017-11-17 17:26:48 -08:00
Henry CookandGitHub 7098ebf439 rocket: fix itim GetPropertyByHartId (#1109) 
needs to use RocketTileParams.hartid instead of zipWithIndex
 2017-11-13 19:25:20 -08:00
Henry CookandGitHub d096fd206b coreplex: WithStatelessBridge => WithIncoherentTiles (#1092) 2017-11-07 13:47:56 -08:00
Henry CookandWesley W. Terpstra b48ab985d0 coreplex: RocketTileWrapper now HasCrossingHelper 2017-10-26 13:04:32 -07:00
Henry CookandWesley W. Terpstra 9fe35382ea sbus: tile adapters in sbus scope 2017-10-26 13:04:32 -07:00
Henry CookandWesley W. Terpstra 95a2e6ef27 coreplex: improve tile attachment adapters 2017-10-26 13:04:32 -07:00
Henry CookandGitHub 1852ccd8f3 Merge pull request #1053 from freechipsproject/resource-cacheable 
tilelink: cacheable resource permission
 2017-10-12 17:49:49 -07:00
Henry Cook ad243ef9f5 tilelink: cacheable resource permission now reports whether a address space could possibly be cached, even if no visible adapters make it so 2017-10-12 13:49:40 -07:00
Henry CookandGitHub ad543e5bb6 Merge pull request #1050 from freechipsproject/uncacheable-tims 
rocket: TIMs should never be cached
 2017-10-12 13:04:00 -07:00
Henry Cook 66e4bfc2d9 rocket: TIMs should never be cached 2017-10-11 18:22:52 -07:00
Henry CookandGitHub b64609bfe8 Merge pull request #1039 from freechipsproject/tile-crossing-params 
Improvements wrt connecting RocketTiles to SystemBus
 2017-10-11 17:12:03 -07:00
Henry CookandGitHub 024ccd8ac2 Merge pull request #1048 from freechipsproject/local_int_hookup 
Correctly hook up the Local Interrupts into the Coreplex.
 2017-10-11 17:08:24 -07:00
Henry Cook 60934ac622 coreplex: TilePortParams use BasicBusBlockers 2017-10-11 13:36:46 -07:00
Henry Cook 2dbe882e58 tilelink: add BasicBusBlocker device 2017-10-11 13:36:42 -07:00
Henry Cook 9f8e3d8879 tilelink: BusBypass can be sent to DeadlockDevice 2017-10-11 12:45:36 -07:00
Henry Cook ec056535dc tilelink: add DeadlockDevice 2017-10-11 12:44:23 -07:00
Henry Cook 329a5c35d4 tilelink: unsafe cache cork discards outer d.sink 2017-10-11 00:30:51 -07:00
Henry Cook 1240cb275c coreplex: TilePortParams formatting 2017-10-11 00:29:11 -07:00
Henry CookandWesley W. Terpstra 75345b6048 rocket: don't remove ports on top module 2017-10-10 21:28:59 -07:00
Henry Cook 1867a5b226 rocket: only cache when AcquireT is possible 2017-10-10 18:06:58 -07:00
Henry Cook 37406706b4 coreplex: move CacheCork in front of SBus 
Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
 2017-10-10 16:24:32 -07:00
Henry Cook 8f5f80f958 coreplex: TileSlavePortParams inject adapters into PBus 2017-10-10 15:25:08 -07:00
Henry Cook 660355004e coreplex: TileMasterPortParams inject adapters into SBus 2017-10-10 15:02:50 -07:00
Henry Cook 9026646459 coreplex: first cut at using RocketCrossingParams 2017-10-10 12:02:04 -07:00
Henry CookandGitHub 9040d921b5 Merge pull request #1031 from freechipsproject/non-contiguous-hartids 
Miscellaneous multicore cleanup
 2017-10-05 12:44:31 -07:00
Henry Cook 8da7aabd51 tile: supply hartid from RocketTileParams 
make WithNCores partial configs override rather than append more tiles
 2017-10-05 00:31:53 -07:00
Henry Cook 45581e60f0 Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid" 
This reverts commit 5232a29d7d, reversing
changes made to a2dc13669a.
 2017-10-05 00:26:44 -07:00
Henry CookandGitHub 5232a29d7d Merge pull request #1027 from freechipsproject/dont-touch-hartid 
Make use of the new DontTouch annotation
 2017-10-03 12:55:34 -07:00
Henry Cook d33737802a util: add DontTouch trait with dontTouchPorts method 2017-10-02 19:36:34 -07:00
Henry Cook aa3a18222c HellaCache: users like to peep resp.data and resp.addr 2017-10-02 19:36:30 -07:00
Henry Cook cedfb0e784 coreplex: dontTouch the rocket_tile_inputs wire 
which contains hartid.
 2017-10-02 19:36:10 -07:00
Henry CookandGitHub 547bdc2b5b diplomacy: standardize sram device resource naming (#1022) 2017-09-29 14:52:26 -07:00
Henry CookandGitHub 33b46af806 Merge pull request #1007 from freechipsproject/tl-error 
Tl error
 2017-09-27 16:22:32 -07:00
Henry CookandGitHub 05112b49a3 Merge branch 'master' into tl-error 2017-09-27 14:50:17 -07:00
Henry CookandGitHub 652d57291c Merge pull request #1018 from freechipsproject/refine-trace-port 
Separate interrupt bit from cause field in trace bundle
 2017-09-27 14:46:27 -07:00
Henry CookandGitHub 5d08b37dab Merge pull request #1019 from freechipsproject/move-rocket-int-sync 
Move rocket output interrupt syncronizers
 2017-09-27 14:46:02 -07:00
Henry Cook f48bf2ac2f rocket: connect uncrossed output interrupts 2017-09-27 12:53:19 -07:00
Henry CookandGitHub 45d26ea130 Merge pull request #1015 from freechipsproject/coherence-manager 
coreplex: clean up coherence manager attachment point
 2017-09-26 11:09:48 -07:00
Henry Cook 9d5e96672e coreplex: clean up coherence manager attachment point 2017-09-25 18:07:51 -07:00
Henry CookandGitHub 5662d1de0b Merge pull request #1012 from freechipsproject/halt-and-catch-fire 
Halt and Catch Fire
 2017-09-22 09:30:30 -07:00
Henry Cook 81e136aa37 rocket: give l2 tlb a nice name 2017-09-21 18:13:39 -07:00
Henry Cook 30c8c8c517 Revert "try to give seqmems clearer names" 
This reverts commit 8db5bbbae0.

This attempt at clarification instead results in confusing generated verilog like:
`dcache_data_arrays_0 icache_data_arrays_0 (...);`
because of deduplication of identically dimensioned SRAMs...
 2017-09-21 18:02:32 -07:00
Henry Cook e0b9f9213a make halt_and_catch_fire Optional 2017-09-21 14:58:47 -07:00
Henry Cook 28b635e721 tile: add halt_and_catch_fire signal 
for unrecoverable / fatal errors
 2017-09-21 14:58:47 -07:00
Henry Cook a887baa615 rocket: base trait for reporting ecc errors 2017-09-21 14:58:47 -07:00
Henry CookandGitHub 323a207bdd Merge pull request #1005 from freechipsproject/trace 
Rename trace.addr -> iaddr
 2017-09-20 15:34:45 -07:00
Henry CookandGitHub 1cb91eed41 Merge pull request #1003 from freechipsproject/ma-fetch 
Don't write badaddr on misaligned fetch exceptions
 2017-09-20 14:28:26 -07:00
Henry CookandGitHub 00cf089350 Merge pull request #1002 from freechipsproject/trace 
Add instruction-trace port
 2017-09-20 11:50:40 -07:00
Henry CookandGitHub 57e8fe0a6b Merge pull request #1000 from freechipsproject/name-seqmems 
try to give seqmems clearer names for use with external tools
 2017-09-19 17:59:00 -07:00
Henry Cook 8db5bbbae0 try to give seqmems clearer names 2017-09-19 13:41:11 -07:00
Henry CookandGitHub 9b75dd7e5b Merge branch 'master' into test_mode_reset 2017-09-15 17:26:11 -07:00
Henry CookandGitHub e8702e2687 Merge pull request #989 from freechipsproject/config-cleanups 
Clean up various Configs/Fields/Params
 2017-09-15 13:45:15 -07:00
Henry Cook e50d14415e tilelink: more verbose requires 2017-09-13 11:25:42 -07:00
Henry Cook 56dae946b6 coreplex: MemoryBusParams.beatBytes also based on XLen 2017-09-13 11:25:42 -07:00
Henry Cook b86f4b9bb7 config: use Field defaults over Config defaults 
Also rename some keys that had the same class name as their value's class name.
 2017-09-13 11:25:42 -07:00
Henry Cook a7540d35b7 ports: use BigInts instead of Longs and the new x"..." context 2017-09-13 11:25:42 -07:00
Henry Cook 37c5af1c0d diplomacy: add x"..." string context 
Enables hex address literals containing underscores.
Converts them to BigInts.
 2017-09-13 11:25:42 -07:00
Henry CookandGitHub 063ca0ed4a Merge pull request #983 from freechipsproject/kill-paddrbits 
Remove global fields PAddrBits and ResetVectorBits
 2017-09-11 12:51:10 -07:00
Henry Cook 9c0bfbd500 tile: remove global Field ResetVectorBits 
Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
 2017-09-08 14:50:59 -07:00
Henry Cook 3133c321b7 scratchpad: remove dependency on HasCoreParameters 2017-09-08 13:55:40 -07:00
Henry Cook e46aeb7342 tile: remove PAddrBits in favor of SharedMemoryTLEdge 2017-09-08 13:53:36 -07:00
Henry CookandWesley W. Terpstra a902e15987 pbus: clarify that we are adding buffers when attaching to sbus 2017-09-05 15:03:38 -07:00
Henry CookandWesley W. Terpstra 8fc4d78c84 frontbus: provide fifofixer on the side of the front bus where masters connect 2017-09-05 15:03:38 -07:00
Henry CookandWesley W. Terpstra 3bde9506c6 coreplex: allow buffer chains on certain bus ports 2017-09-05 15:03:36 -07:00
Henry Cook 32cb358c81 coreplex: include optional tile name for downstream name stabilization 2017-08-30 15:48:55 -07:00