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Author	SHA1	Message	Date
Wesley W. Terpstra	eac4d44131	tilelink2: don't apply HintHandler to B=>C by default	2016-09-05 20:58:39 -07:00
Wesley W. Terpstra	cc8112d02e	tilelink2: pass E through the HintHandler	2016-09-05 20:58:39 -07:00
Wesley W. Terpstra	a72f7115ae	tilelink2: optimize support testing circuits	2016-09-05 20:58:39 -07:00
Wesley W. Terpstra	f0cfd81820	tilelink2: add an adapter to add support for Hints to devices	2016-09-05 20:58:39 -07:00
Wesley W. Terpstra	5f6ca0bd0d	tilelink2: rename wmask => mask since it also applies to reads	2016-09-05 20:58:39 -07:00
Wesley W. Terpstra	7347b0c4dd	tilelink2: TLLegacy converts from legacy TileLink to TileLink2	2016-09-05 20:58:39 -07:00
Wesley W. Terpstra	fa472e38fb	tilelink2: monitor error line legality	2016-09-05 20:58:39 -07:00
Wesley W. Terpstra	edb17d1e34	tilelink2: document allowed (and required) response messages	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	ec1f901a38	tilelink2: move error from type into Bundle and add HintAck ... We need Grant with errors too. We also want to match response type to request type more easily.	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	534d7f6eb6	tilelink2: implement SRAM manager	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	32894a8e20	tilelink2: transfers must never exceed 4kB	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	dd27a60daa	tilelink2: use consistent in/out ports for TLSimpleFactories	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	1a87eef3e2	tilelink2: add atomic message types	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	5f7711a0c0	tilelink2: add an intermediate type for simple factories	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	967d8f108c	tilelink2: support ready-valid enqueue+dequeue on register fields	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	77cf186cf0	tilelink2: make bundle parameterization reusable	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	594850eaae	tilelink2: assert-fail on something more user understandable	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	dc1164a996	tilelink2: defer bundle construction until after Module base class instantiated	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	18e149098a	tilelink2: connect abstract register-based modules to TileLink	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	917a9c8e5d	tilelink2: forward declarations for message constructors	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	4649c42f50	tilelink2: use a new type in the signature of null-parameter Bundle methods	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	0ff33a31a4	tilelink2: add a stub SRAM manager	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	a87c2d13e2	tilelink2: include an abstract definition for register mapped devices	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	3a441d853f	tilelink2: clarify that fifoId only applies to accesses (not hints)	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	4b99bd3be1	tilelink2: mask out unnecessary address bits	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	e24ba61754	tilelink2: distinguish two levels of uncacheability	2016-09-05 20:58:38 -07:00
Wesley W. Terpstra	e506309998	tilelink2: prototype crossbar implementation	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	34f65938b6	tilelink2: add a TLBundle constructor	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	1cd85ff050	tilelink2: add some bundle introspection to scaffold the xbar	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	9c62f5d9c1	tilelink2: shave off a few more firrtl monitor lines	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	af29595979	tilelink2: eliminate common subexpressions in Monitor to reduce firrtl output	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	d7e839280f	tilelink2: include legal message monitor	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	492a38aedc	tilelink2: only accesses can have errors (release must make forward progress)	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	6599bcb77b	tilelink2: statically check Operations are remotely plausible	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	8cff45f254	tilelink2: use byte-aligned addressing ... This makes it possible to fully validate user input in a monitor. We will override the lower bits with constant 0s in the TL connect.	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	45e152e97e	tilelink2: include Operation constructors	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	5b10c1a328	tilelink2: arithmetic and logical atomics must be distinct (priv spec 3.5.3)	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	8592cbf0e3	tilelink2: Message and Permisison types from Henry	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	9a460322da	tilelink2: add synthesizable test methods for Parameters	2016-09-05 20:58:37 -07:00
Wesley W. Terpstra	7328b55abd	tilelink2: first cut at parameterization	2016-09-05 20:58:37 -07:00
Howard Mao	59a2e6a4dc	Merge pull request #244 from ucb-bar/compelete-dramsim-removal ... remove remaining dramsim2 files	2016-09-05 15:05:38 -07:00
Colin Schmidt	ba4b3e14cc	remove remaining dramsim2 files	2016-09-04 17:25:24 -07:00
Howard Mao	8906097250	have Travis cache the entire verilator directory	2016-09-04 15:05:30 -07:00
Howard Mao	a7f79aa409	get rid of TileLinkMemorySelector	2016-09-04 10:55:19 -07:00
Howard Mao	f0ab6d0214	tie off finish signals in tilelink wrapper and unwrapper	2016-09-04 10:55:19 -07:00
Howard Mao	66de89c4db	allow fixed priority routing in Junctions arbiters	2016-09-04 10:55:19 -07:00
Howard Mao	efe8670283	allow Serializer/Deserializer to work with arbitrary Chisel data types	2016-09-04 10:55:19 -07:00
Howard Mao	b9b79e4fb6	get rid of AtoS RTL	2016-09-04 10:55:19 -07:00
Howard Mao	f34843f1b9	fix assignment of incoherent vector	2016-09-04 10:12:16 -07:00
Yunsup Lee	a4c1942958	flatten Coreplex module hierarchy	2016-09-02 17:45:08 -07:00